Reliability and Security of AI Hardware
Affiliation: INRIA, University of Rennes (FR)
Speakers: Paolo Rech (University of Trento), Ernesto Sanchez (Politecnico di Torino), Vincent Meyers (Karlsruhe Institute of Technology), Russell Tessier (University of Massachusetts Amherst),
SS1.1: Ernesto Sanchez (Politecnico di Torino) - "Current Challenges and Solutions for Assessing the Reliability of Hardware Platforms for Machine Learning"
SS1.2: Paolo Rech (University of Trento) - “Characterizing and Mitigating Radiation-Induced Faults on Machine Learning Accelerators"
SS1.3: Russell Tessier (University of Massachusetts Amherst) - “Remote Attacks and Countermeasures on FPGA-based Neural Networks Used for Image Processing"
SS1.4: Vincent Meyers (Karlsruhe Institute of Technology) - “Training-Based Hiding Countermeasures against Input Recovery Side-Channel Attacks on Neural Networks"
In recent years, AI systems have achieved revolutionary capabilities, providing intelligent solutions that surpass human skills in many cases. However, such capabilities come with power-hungry computation workloads. Therefore, the implementation of hardware acceleration becomes as fundamental as the software design to improve energy efficiency, silicon area, and latency of AI systems. Existing traditional computing platforms are no longer sufficient to bridge the gap between algorithmic innovation and hardware design. Thus, innovative hardware platforms (GPUs, FPGAs, dedicated ASICs, in-memory accelerators), architectures (e.g., systolic arrays, dataflow-based), and compiler-level approaches (e.g. Apache TVM, Intel nGraph) have been used to accelerate AI workloads. Crucially, innovative AI acceleration platforms are being adopted in application domains for which dependability must be paramount, such as autonomous driving, healthcare, banking, and industry 4.0. Unfortunately, the complexity of both AI software and hardware makes the dependability evaluation and improvement extremely challenging. Studies on both the security and reliability of AI systems have been conducted. For example, side-channel attacks have been proven powerful in retrieving information from the AI HW platform; also, vulnerability assessments of AI hardware acceleration platforms to random faults and related countermeasures have been proposed. This special session proposes an in-depth analysis of reliability and security threats and presents possible efficient countermeasures for AI systems. The four talks in the session will explore different dependability aspects, spanning the assessment of AI hardware reliability to radiation-induced transient faults, the consequences of faults propagation through the microarchitecture to identify and protect potentially vulnerable parts, the analysis of security threats to AI hardware (such as side-channel attacks), and investigate different possible countermeasures to be applied at training time, compile time, or run time.
The first talk is centered on Current Challenges and Solutions for Assessing the Reliability of Hardware Platforms for Machine Learning. In this talk, we review and analyze the current approaches and trends to assess and characterize the vulnerability to hardware faults of AI-based systems. Firstly, the technical challenges in assessing the reliability at different abstraction levels of ML-based systems are discussed; then, the identification of fault vulnerability issues related to the most relevant components within large hardware accelerators (e.g., GPUs) is presented, highlighting how these problems can lead to the increase of silent data corruptions in AI applications. Finally, we provide an overview of several opportunities to enhance fault protection and mitigation on modern machine learning accelerators.
The second talk focuses on Characterizing and Mitigating Radiation-Induced Faults on Machine Learning Accelerators. The increased hardware resources and intrinsic parallelism of machine learning (ML) accelerators drastically change how radiation-induced faults propagate from the transistor level to the application output. A single fault, for instance, can impact several computing elements, jeopardizing the inference calculation and leading to misclassifications or misdetections. Radiation experiments are the most realistic way to evaluate the ML models' reliability, estimating their error rate and characterizing how faults can reduce the accuracy of ML applications. We discuss how radiation-induced faults on accelerators such as GPUs, TPUs, and FPGAs can severely reduce the accuracy of complex ML models. We show that a single radiation-induced fault can corrupt multiple threads or processing elements' output, compromising the neural network's ability to deliver an inference correctly.
Moving on to security aspects, the third talk will focus on Remote Attacks and Countermeasures on FPGA-based Neural Networks Used for Image Processing. In this talk, we examine the sensitivity of minor on-FPGA voltage fluctuations detections and techniques that can be used to avoid the leakage of image information. Countermeasures can be deployed at both compile time and run time, and often multiple techniques can be combined together. By characterizing the threat and analyzing countermeasures, the security of cloud FPGA neural network implementations of image processing algorithms can be better understood. We will also describe how these techniques could be applied to other FPGA ML implementations. Experimental results from execution on AWS EC2 F1 nodes will be included.
Finally, the fourth talk will address Training-Based Hiding Countermeasures against Input Recovery Side-Channel Attacks on Neural Networks. Recent work has shown how severe the threat of side-channel attacks on neural networks running on FPGA hardware is. By measuring tiny voltage fluctuations in the FPGA's power grid during a neural network inference using a specially designed circuit deployed on the FPGA, an attacker is able to extract the input of the neural network. A number of countermeasures to mitigate or prevent this problem are known, but these typically come along with a significant price tag in terms of time, energy, and memory consumption. In this talk, we present an innovative countermeasure for the aforementioned threat using a training-based approach. In a nutshell, we train the classifier running on an FPGA to fulfill two objectives at the same time: perform the actual classification and minimize the leakage through the side channel. To do so, we use a neural network that simulates the leakage given the input and weights of the original neural network. Our countermeasure requires more time for training since it is needed to measure several thousand traces on an FPGA. However, due to its design, our approach only modifies the weights of the neural network and, thus, does not introduce any additional runtime cost in terms of space or time consumption for inference in comparison to the unprotected network overlay.
Paolo Rech (University of Trento) is an associate professor at Università di Trento, in Italy, a Rosen Scholar Fellow at the Los Alamos National Laboratory, and he received the Impact in Society award from the Rutherford Appleton Laboratory, UK, and the Marie Curie Fellowship. His main research interests include the evaluation and mitigation of radiation-induced effects in autonomous vehicles for automotive applications and space exploration, in large-scale HPC centers, and quantum computers.
Ernesto Sanchez (Politecnico di Torino) is an associate professor at the Politecnico di Torino, Italy. His research interests include digital circuits and systems reliability, evolutionary computation, and artificial intelligence. Sanchez received a Ph.D. in computer engineering from the Politecnico di Torino. He is a Senior Member of IEEE.
Vincent Meyers received his M.Sc. in Computer Science from Karlsruhe Institut of Technology (KIT) in 2022. His master thesis was focused on reverse-engineering folded neural network architecture.
Since June 2022, he is a Ph.D. student at the CDNC group of Prof. Mehdi B. Tahoori at Karlsruhe Institute of Technology.
His current research interests are in hardware security, with a focus on side-channel attacks and defense mechanisms for neural network accelerators.
Russell Tessier (University of Massachusetts Amherst) is a professor of electrical and computer engineering at the University of Massachusetts Amherst. Dr. Tessier has performed research in FPGAs and reconfigurable computing for over 30 years. He was a founder of Virtual Machine Works, a logic emulation company that is now owned by Siemens. His current research interests include embedded security, cloud FPGAs, and system verification.
Marcello Traiola (Inria Centre at Rennes University) is a faculty Research Scientist at Inria Centre of Rennes University in France. His main research topics are emerging computing paradigms, with a special interest in hardware reliability, testing, and design. He serves as Review and Programme Operations Chair of DATE (‘23-’25) and General co-chair of IOLTS 2024. Marcello organized a special session at IOLTS 2023 and was the Special Session Chair of IOLTS 2022 and DTIS 2021.
Angeliki Kritikakou (University of Rennes) is an Associate Professor at the University of Rennes in France and a junior member of Institut Universitaire de France (IUF), holding an Innovation Chair. Her research interests include fault tolerance, embedded systems, real-time systems, mixed-critical systems, hardware/software co-design, and low-power design. Among others, Angeliki serves as General co-chair of IOLTS 2024, and was Hot Topics Day Chair at RTSS 2023. She organized a special session at IOLTS 2022.
LAST-MODIFIED:20240521T091447Z SEQUENCE:5959406 LOCATION:Johan de Wittlaan 30\, 2517 JR Den Haag\, Zuid-Holland\, Netherlands GEO:52.08989950;4.28243397 X-LOCATION-DISPLAYNAME:Room Gaugain + Dali X-ACCESS:1 X-HITS:706 X-COLOR:3366cc X-SHOW-END-TIME:1 END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Amsterdam:20240521T140000 DTEND;TZID=Europe/Amsterdam:20240521T153000 UID:9ADD81F1-2979-41FD-B200-37659F653CFB SUMMARY:Special Session 2 CREATED:20240313T095213Z DTSTAMP:20240313T095213Z URL:https://ets24.ewi.tudelft.nl/index.php/home/program/conference-program/special-session-2 DESCRIPTION:\NSilent Data Corruption: Test or Reliability Problem?\N \N\NOrganizer: Erik Jan Marinissen, imec (BE)\NModerator: Bram Kruseman, NXP Semiconductors (NL)\NSpeakers: Harish Dixit, Meta (US) Shawn Blanton, Carnegie Mellon University (US) Ben Kaczer, imec (BE)\NRecently, companies such as Google, Meta (Facebook), and MicroSoft reported in the mainstream press about seemingly random errors which, initially undetected (“silently”), had crept into their large cloud data centers. These reports mentioned that very specific instructions were intermitently incorrectly executed, propagated through the operating system, and would potentially manifest themselves as application-level errors. Are the root causes of these so-called silent data errors test escapes and/or reliability issues? Why are they only noticed now? Is that only the case because such large server farms bring together larger numbers of CPUs than ever seen before? And what counter measures can we take against them?\NA. Silent Data Corruptions at Scale\NHarish Dixit, Meta (US)\NSilent data corruptions (SDC) in hardware impact computational integrity for large-scale applications. Sources of corruptions include datapath dependencies, temperature variance, and age among other silicon factors. These errors do not leave any record or trace in system logs. As a result, silent errors stay undetected within workloads, and can propagate across the stack to the applications. Silent errors can result in data loss and can require months of debug engineering time. In our large-scale infrastructure, we have run a vast library of silent error test scenarios across hundreds of thousands of machines in our fleet. This has resulted in hundreds of CPUs detected for these errors, showing that SDCs are a systemic issue across device generations. Based on this experience, we determine that reducing silent data corruption requires not only hardware resiliency and production detection mechanisms, but also robust fault-tolerant software architectures.\NB. Incompatible: Test Quality and Fortuitous Detection\NChris Nigh, Ruben Purdy, Wei Li, Aaron Kuo, Shawn Blanton, Carnegie Mellon University (US) Subhasish Mitra, Stanford University (US)\NSilent data errors (SDEs also sometimes called silent data corruptions (SDCs)) have received a great deal of atention as of late due to their negative impact on enterprises that rely on large farms of reliably-operating compute cores. Recent publications have reported that the root-cause of SDEs include defects within the logic that escape manufacturing testing. An escaped defect is due to its behavior deviating from what is predicted by the models and metrics utilized for test generation. In order to reduce escape, the first step must involve understanding how often and in what manner does defect behavior deviate from the models/metrics used for ATPG. In this work, we describe and demonstrate a methodology for precisely deriving defect behavior from ATE data collected from a failing logic circuit. The gap measured between models/metrics and actual defect behavior for a 14nm industrial test chip is so substantial that we conclude that test quality can only be maintained and improved if fortuitous detection is reduced. In other words, understanding and minimizing the deviations between predicted behavior and actual defect behavior are crucial for enhancing test quality in the context of SDEs.\NC. Intermittent Silent Data Errors: Possible Physical Origins and Implications\NBen Kaczer, Dishant Sangani, Pieter Weckx, Subrat Mishra, Philippe J. Roussel, Erik Jan Marinissen, imec (BE), Georges Gielen, KU Leuven (BE)\NSilent Data Errors (SDE) are likely caused by several distinct underlying effects. It is estimated that ~80% of SDEs are due to time-zero test escapes. Here, we focus on the remaining ~20%, which manifest intermittency and aging, features commonly encountered in the VLSI front-end-of-line (FEOL) reliability domain and linked to FET gate oxide defects. We draw on these parallels to define the main properties of an “archetypal” intermittent SDE fault and explain how such faults could be identified through their characteristic “signatures”. We give examples of fault signatures related to gate-oxide breakdown (BD) and Random Telegraph Noise (RTN). Finally, we propose a “prime and test” screening technique for RTN-related faults.\NBiographies of the Speakers\N\N\NHarish Dattatraya Dixit is a principal engineer at Meta. Harish and team work on reliability, analytics, and performance evaluation for all of deployed fleet of servers. Harish leads the efforts to deal with silent data corruption within Meta infrastructure across CPUs, GPUs, and ASICs, and has been working across different layers of the stack to mitigate the effects of silent data corruption on production applications. Harish has over 20 patent filings across system architecture and communication domains.\N\N\N\NShawn Blanton is the Joseph F. and Nancy Keithley Professor of Electrical and Computer Engineering (ECE) Department at Carnegie Mellon University, where he also serves as the department’s Associate Head of Research. His research interests are housed in the Advanced Chip Testing Laboratory (www.ece.cmu.edu/~actl) and include the design, test, diagnosis, and security of integrated systems. He has published over 200 papers in these areas and has several issued and pending patents. Prof. Blanton has received the National Science Foundation Career Award for the development of a microelectromechanical systems (MEMS) testing methodology, and several industrial faculty awards from companies such as IBM, Qualcomm, Google, Teradyne and CISCO. He is a Fellow of the IEEE, and senior member of the ACM. Professor Blanton served as the Acting Associate Dean of Diversity and Inclusion for the College of Engineering from 2019-2020, and the Interim Vice Provost for Diversity, Equity, and Inclusion for Carnegie Mellon University from 2020-2021. Professor Blanton is the recipient of the 2006 Emerald Award for outstanding leadership in recruiting and mentoring minorities for advanced degrees in science and technology; the 2021 College of Engineering Mentoring Award in recognition of excellence in mentoring of graduates students and junior faculty; and the 2022 National Science of Black Engineer’s Lifetime Achievement in Academia Award for exhibiting career technical excellence and leadership in higher education in a career spanning several years.\N\N\NBen Kaczer is a scientific director in the FEOL reliability group at imec. Dr. Kaczer received the M.S. degree in Physical Electronics from Charles University, Prague, in 1992 and the M.S. and Ph.D. degrees in Physics from The Ohio State University, in 1996 and 1998, respectively. In 1998 he joined imec in Leuven, Belgium, where his activities have included the research of the degradation phenomena and reliability assessment of SiO2, SiON, high-k, and ferroelectric films, planar and multiple gate FETs, circuits, and characterization of Ge, SiGe, III-V, MIM, and TMD devices. He has co-authored more than 600 journal and conference papers and four patent groups related to device and circuit reliability, presented invited papers and tutorials, and received six IEEE International Reliability Physics Symposium (IRPS) Best and Outstanding Paper Awards, two IEEE IPFA Best Paper Awards, and the 2011 IEEE EDS Paul Rappaport Award. In 2019, he was historically the most cited author of IRPS. His h-index on Google Scholar is 64. Dr. Kaczer has served twice as the chair of the Characterization, Reliability and Yield subcommitee of the International Electron Device Meeting (IEDM; 2007 and 2015) and as a member of various subcommitees of the IRPS (2002—2016) and is currently serving as a member of IRPS management commitee (2018—). He was the General Chair of the Semiconductor Interfaces Specialists Conference (SISC; 2006) and continues to act as the conference secretary (2007—). He co-organized the INFOS conference (2005), and served on the INFOS, WoDiM, IPFA, and ICICDT conference commitees. He has served on the Editorial Board of IEEE Journal of Transaction of Electron Devices for three terms (2011—2019). X-ALT-DESC;FMTTYPE=text/html: Organizer: Erik Jan Marinissen, imec (BE)
Moderator: Bram Kruseman, NXP Semiconductors (NL)
Speakers: Harish Dixit, Meta (US) Shawn Blanton, Carnegie Mellon University (US) Ben Kaczer, imec (BE)
Recently, companies such as Google, Meta (Facebook), and MicroSoft reported in the mainstream press about seemingly random errors which, initially undetected (“silently”), had crept into their large cloud data centers. These reports mentioned that very specific instructions were intermitently incorrectly executed, propagated through the operating system, and would potentially manifest themselves as application-level errors. Are the root causes of these so-called silent data errors test escapes and/or reliability issues? Why are they only noticed now? Is that only the case because such large server farms bring together larger numbers of CPUs than ever seen before? And what counter measures can we take against them?
Harish Dixit, Meta (US)
Silent data corruptions (SDC) in hardware impact computational integrity for large-scale applications. Sources of corruptions include datapath dependencies, temperature variance, and age among other silicon factors. These errors do not leave any record or trace in system logs. As a result, silent errors stay undetected within workloads, and can propagate across the stack to the applications. Silent errors can result in data loss and can require months of debug engineering time. In our large-scale infrastructure, we have run a vast library of silent error test scenarios across hundreds of thousands of machines in our fleet. This has resulted in hundreds of CPUs detected for these errors, showing that SDCs are a systemic issue across device generations. Based on this experience, we determine that reducing silent data corruption requires not only hardware resiliency and production detection mechanisms, but also robust fault-tolerant software architectures.
Chris Nigh, Ruben Purdy, Wei Li, Aaron Kuo, Shawn Blanton, Carnegie Mellon University (US) Subhasish Mitra, Stanford University (US)
Silent data errors (SDEs also sometimes called silent data corruptions (SDCs)) have received a great deal of atention as of late due to their negative impact on enterprises that rely on large farms of reliably-operating compute cores. Recent publications have reported that the root-cause of SDEs include defects within the logic that escape manufacturing testing. An escaped defect is due to its behavior deviating from what is predicted by the models and metrics utilized for test generation. In order to reduce escape, the first step must involve understanding how often and in what manner does defect behavior deviate from the models/metrics used for ATPG. In this work, we describe and demonstrate a methodology for precisely deriving defect behavior from ATE data collected from a failing logic circuit. The gap measured between models/metrics and actual defect behavior for a 14nm industrial test chip is so substantial that we conclude that test quality can only be maintained and improved if fortuitous detection is reduced. In other words, understanding and minimizing the deviations between predicted behavior and actual defect behavior are crucial for enhancing test quality in the context of SDEs.
Ben Kaczer, Dishant Sangani, Pieter Weckx, Subrat Mishra, Philippe J. Roussel, Erik Jan Marinissen, imec (BE), Georges Gielen, KU Leuven (BE)
Silent Data Errors (SDE) are likely caused by several distinct underlying effects. It is estimated that ~80% of SDEs are due to time-zero test escapes. Here, we focus on the remaining ~20%, which manifest intermittency and aging, features commonly encountered in the VLSI front-end-of-line (FEOL) reliability domain and linked to FET gate oxide defects. We draw on these parallels to define the main properties of an “archetypal” intermittent SDE fault and explain how such faults could be identified through their characteristic “signatures”. We give examples of fault signatures related to gate-oxide breakdown (BD) and Random Telegraph Noise (RTN). Finally, we propose a “prime and test” screening technique for RTN-related faults.
Harish Dattatraya Dixit is a principal engineer at Meta. Harish and team work on reliability, analytics, and performance evaluation for all of deployed fleet of servers. Harish leads the efforts to deal with silent data corruption within Meta infrastructure across CPUs, GPUs, and ASICs, and has been working across different layers of the stack to mitigate the effects of silent data corruption on production applications. Harish has over 20 patent filings across system architecture and communication domains.
Organizer: Michele Portolan, Grenoble-INP (FR), Martin Keim, Siemens Digital Industries Software (US), and Jeff Rearick, Digital Industries Software (CA)
Moderator: Erik Larsson, Lund University (SE)
Speakers: Hans Martin von Staudt (Renesas), secretary of the IEEE P1687.2 WG, Michele Portolan (Grenoble-INP), secretary of the IEEE P1687 WG, J-F Cote (Siemens Digital Industries Software), member of the IEEE P1687 and IEEE P1687.1 WGs
As PDL has been developed to be syntactically compatible with TCL, it is possible to use an interpreter to enhance test routines with programming features, such as variables, flow control, etc.. Moreover, one of the big novelties of IEEE 1687 is the native support of Interactive Behaviour thanks to the PDL-1 instruction set. The most important is “iGetReadData”, which returns the last data value read from the target register, which can then be used inside the TCL Interpreter. However, it is not quite clear what “Interactive Behaviour” actually means and how it gets from simulation to automatic test equipment. IEEE 1687 is a “descriptive” standard, so there is no provision or limitation on the way the test routines will be executed and if and how they will interact with the System Under Test.
In this special session, we will delve into this issue by presenting the points of view and expectations of three actors: the final user, the practical EDA provider, and the idealistic academic. The idea is to present three different visions, highlighting not only their synergies but also their differences to stimulate a constructive discussion.
Jean-François Côté is a technical fellow with Siemens Digital Industries Software and is the main architect of the Tessent Shell platform.
His interests include design automation and chip design. He received a key contributor award for the IEEE1687-2014 standard and continues to be an active contributor to the next revision. J-F has a Master in electrical engineering from McGill University, Canada.
Michele Portolan is a Senior Associate Professor at the Grenoble-INP school of Electronics Engineering since 2013. Prior to that, he was a Member of Technical Staff at Bell Labs in Ireland and France. He is the author of several journal and research paper, and has been granted 20 US and EU patents. His main research interest are Design for Test, Reliability and next-generation Test Standards, with a particular emphasis on their interaction with neighboring domains such as Security and Mixed-Signal.
Hans Martin Obtained Diploma degree in Electronics from Dortmund University in 1988
Held various positions in electronics and ASIC design before joining Dialog Semiconductor (now Renesas) in 2000
Head of Project Management until 2003
Responsible for Test and Product Engineering until 2007
Since then, developing and driving implementation of Analog and Digital DfT strategy at Renesas with his team.
A track record of 11 granted patents and 15 IEEE publications. Holder of ITC's Best Paper Award.
Special Interests (among everything to make Renesas' DfT work):
- Trimming, self-trim, self-test
- Analog test automation, Secretary of the IEEE WG P1687.2
- Non-volatile memory
LAST-MODIFIED:20240521T091523Z SEQUENCE:5959326 LOCATION:Johan de Wittlaan 30\, 2517 JR Den Haag\, Zuid-Holland\, Netherlands GEO:52.08989950;4.28243397 X-LOCATION-DISPLAYNAME:Room Gaugain + Dali X-ACCESS:1 X-HITS:687 X-COLOR:3366cc X-SHOW-END-TIME:1 END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Amsterdam:20240523T091500 DTEND;TZID=Europe/Amsterdam:20240523T101500 UID:9A1A4A5C-48CF-42B7-AB1C-0F3220764CFB SUMMARY:Special Session 4 CREATED:20240313T095345Z DTSTAMP:20240313T095345Z URL:https://ets24.ewi.tudelft.nl/index.php/home/program/conference-program/special-session-4 DESCRIPTION:\NTest-Fleet Optimization Using Machine Learning\N \N\NOrganizer: Krishnendu Chakrabarty, Arizona State University (US)\NModerator: Jerzy Tyszer, Poznań University of Technology (PL)\NSpeakers: Dr. Andrew Dove (NI), Prof. Krishnendu Chakrabarty, Arizona State University (US). \NThis special session will introduce the ETS audience to a test planning problem (and emerging solution) that is relevant to many companies making up the semiconductor test ecosystem, for both validation and production. It includes two talks to be presented by speakers from industry and academia. The first talk will be from NI (now part of Emerson) and the second talk will be from Arizona State University.\NAbstract: \NNI’s Global Operations solution is deployed in many OSATs1, foundries, and IDM2 test floors for data collection and applying techniques to improve yield, quality, and efficiency of the test operations. The connected software infrastructure from NI utilizes real-time test data from the ATE as well as MES3 data on the tested lots. The semiconductor industry is constantly exploring new ways to leverage these offerings by using advanced technologies to streamline test and validation. As part of an ongoing collaboration, NI and Arizona State University are developed a smart scheduling solution based on machine learning that can be used to optimize equipment utilization and overall efficiency of the test process. In this special session we will describe the modeling techniques and solutions developed for test scenarios in both validation labs and production facilities.We will first describe how the scheduling problem can be mathematically formulated as a constraint optimization problem (COP) by defining the tardiness objective and various involved constraints as linear equalities and inequalities. We have implemented this formulation following the framework of Mixed Integer Linear Programming (MILP) and solved it using the SCIP solver, which uses branch-and-bound algorithms. As the time taken to solve the MILP grows exponentially with the number of jobs, operations, testers and configurations, this methodology is infeasible for use in the real-world; nevertheless, solutions produced by it for small problem instances are being used as baselines for evaluating the effectiveness of the more proposed methodologies being developed.We have converted the test scheduling problem to a sequential decision-making process with two agents. We have mathematically formulated this process as a partially observable stochastic game (POSG) which is a variation of Markov Decision Process (MDP) with partial observability. We have implemented a simulator that allows us to study various facets of the test scheduling problem following this POSG formulation. We have defined the corresponding observation, action spaces and reward functions that optimize our objective in this solution approach based on reinforcement learning. We have implemented a number of greedy dispatching rules to generate schedules which we have used along with the MILP solution as baselines to compare with the solution produced by our policies. We have observed that the schedules produced by our policies are significantly better than the greedy dispatching rules in terms of the final tardiness. In addition, our schedules outperform the MILP schedules when we run the SCIP solver for a reasonable amount of CPU time.\NWe will present results for realistic test cases from the production environment to validate the above solutions. We believe that this special session, the first of its type at ETS, will generate considerable interest among the attendees and lead to new collaborations and a community of researchers, and broaden the appeal of the conference to a new group of academics and industry practitioners. \NBiography: \NAndrew Dove is a Distinguished Engineer in the Long Term Innovation group at NI. He holds a master's degree in Astronomy from The University of Texas at Austin and a bachelor's degree in physics from Oxford University. He has over 35+ years of technology industry experience as technical leader for a wide range of applications in process control and test and measurement. \NKrishnendu Chakrabarty received his B.Tech from IIT Kharagpur, India, and M.S.E.and Ph.D. degrees from University of Michigan at Ann Arbor, MI, USA. A Fulton Professor of Microelectronics in the SECEE at Arizona State University (ASU), the CTO of the Department of Defense Microelectronics Commons Southwest Advanced Prototyping (SWAP) Hub and the Director of the ASU Center on Semiconductor Microelectronics. He is a Fellow of ACM and AAAS, and a Golden Core Member of the IEEE Computer Society. X-ALT-DESC;FMTTYPE=text/html:
Organizer: Krishnendu Chakrabarty, Arizona State University (US)
Moderator: Jerzy Tyszer, Poznań University of Technology (PL)
Speakers: Dr. Andrew Dove (NI), Prof. Krishnendu Chakrabarty, Arizona State University (US).
This special session will introduce the ETS audience to a test planning problem (and emerging solution) that is relevant to many companies making up the semiconductor test ecosystem, for both validation and production. It includes two talks to be presented by speakers from industry and academia. The first talk will be from NI (now part of Emerson) and the second talk will be from Arizona State University.
NI’s Global Operations solution is deployed in many OSATs1, foundries, and IDM2 test floors for data collection and applying techniques to improve yield, quality, and efficiency of the test operations. The connected software infrastructure from NI utilizes real-time test data from the ATE as well as MES3 data on the tested lots. The semiconductor industry is constantly exploring new ways to leverage these offerings by using advanced technologies to streamline test and validation. As part of an ongoing collaboration, NI and Arizona State University are developed a smart scheduling solution based on machine learning that can be used to optimize equipment utilization and overall efficiency of the test process. In this special session we will describe the modeling techniques and solutions developed for test scenarios in both validation labs and production facilities.
We will first describe how the scheduling problem can be mathematically formulated as a constraint optimization problem (COP) by defining the tardiness objective and various involved constraints as linear equalities and inequalities. We have implemented this formulation following the framework of Mixed Integer Linear Programming (MILP) and solved it using the SCIP solver, which uses branch-and-bound algorithms. As the time taken to solve the MILP grows exponentially with the number of jobs, operations, testers and configurations, this methodology is infeasible for use in the real-world; nevertheless, solutions produced by it for small problem instances are being used as baselines for evaluating the effectiveness of the more proposed methodologies being developed.
We have converted the test scheduling problem to a sequential decision-making process with two agents. We have mathematically formulated this process as a partially observable stochastic game (POSG) which is a variation of Markov Decision Process (MDP) with partial observability. We have implemented a simulator that allows us to study various facets of the test scheduling problem following this POSG formulation. We have defined the corresponding observation, action spaces and reward functions that optimize our objective in this solution approach based on reinforcement learning. We have implemented a number of greedy dispatching rules to generate schedules which we have used along with the MILP solution as baselines to compare with the solution produced by our policies. We have observed that the schedules produced by our policies are significantly better than the greedy dispatching rules in terms of the final tardiness. In addition, our schedules outperform the MILP schedules when we run the SCIP solver for a reasonable amount of CPU time.
We will present results for realistic test cases from the production environment to validate the above solutions. We believe that this special session, the first of its type at ETS, will generate considerable interest among the attendees and lead to new collaborations and a community of researchers, and broaden the appeal of the conference to a new group of academics and industry practitioners.
Andrew Dove is a Distinguished Engineer in the Long Term Innovation group at NI. He holds a master's degree in Astronomy from The University of Texas at Austin and a bachelor's degree in physics from Oxford University. He has over 35+ years of technology industry experience as technical leader for a wide range of applications in process control and test and measurement.
Krishnendu Chakrabarty received his B.Tech from IIT Kharagpur, India, and M.S.E.and Ph.D. degrees from University of Michigan at Ann Arbor, MI, USA. A Fulton Professor of Microelectronics in the SECEE at Arizona State University (ASU), the CTO of the Department of Defense Microelectronics Commons Southwest Advanced Prototyping (SWAP) Hub and the Director of the ASU Center on Semiconductor Microelectronics. He is a Fellow of ACM and AAAS, and a Golden Core Member of the IEEE Computer Society.
LAST-MODIFIED:20240517T092929Z SEQUENCE:5614544 LOCATION:Johan de Wittlaan 30\, 2517 JR Den Haag\, Zuid-Holland\, Netherlands GEO:52.08989950;4.28243397 X-LOCATION-DISPLAYNAME:Room Gaugain + Dali X-ACCESS:1 X-HITS:609 X-COLOR:3366cc X-SHOW-END-TIME:1 END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Amsterdam:20240523T110000 DTEND;TZID=Europe/Amsterdam:20240523T123000 UID:DEC5F5CA-49C3-407B-804C-711C461D199C SUMMARY:Special Session 5 CREATED:20240313T095426Z DTSTAMP:20240313T095426Z URL:https://ets24.ewi.tudelft.nl/index.php/home/program/conference-program/special-session-5 DESCRIPTION:\NTesting for Reliability of Modern Power Electronic Components\N \N\NOrganizer: Francesco Iannuzzo, Aalborg University (DK)\NModerator: Francesco Iannuzzo, Aalborg University (DK)\NSpeakers: \N\N\NKim A. Schmidt (FORCE Technology, Hoersholm, Denmark): "From measurements to accelerated testing – a case with vibration & shock"\N\N\NFrancesco Iannuzzo (AAU Energy, Aalborg University, Denmark): “Testing for Abnormal Conditions of Modern Power Electronic Devices”\N\N\NGolta Khatibi (Institute for Chemical Technologies and Analytics, TU Wien, Austria): “Innovative testing techniques for bond-wire fatigue in power electronic components”\N\N\NThomas Ebel (University of Southern Denmark, Denmark): “Comparison of a New Characterization Technique of Electrical Properties of Radial Aluminum Electrolytic Capacitors versus Traditional Characterization Methods”\N\N\NSession’s scope and topic(s):Power Electronics is an essential technology for the green transition. This is due to the intrinsically stochastic nature of renewable energy sources as well as the need for storage of vast amounts of energy, e.g., for transportation, in the form of electricity. For this reason, the reliability of power electronic components has become crucial in the last decade. This special session addresses the state of the art and the issues of the modern testing approaches for the reliability assessment of power electronic components.\NObjectives and relevance of the proposed session to ETS:\NThe special session (SS) is intended to bridge the gap between the testing community (TC) and the power electronic devices community (PEDC), with an expectedly obvious benefit for both of them. The SS is organized by Prof. F. Iannuzzo, Aalborg University, Denmark, who is active in PEDC, and addresses an audience primarily belonging to the TC.\NFormat of the session:\NThe SS has the form of four speeches, i.e., 2 x 30 minutes and 2 x 15 minutes, including Q&A, where four different speakers from the PEDC present some key challenges within the testing for reliability of power electronic components.\NBiographies of the Speakers:\NThomas Ebel: Prof. Thomas Ebel is currently a Professor of Advanced Capacitor Technologies at the University of Southern Denmark (SDU), Denmark. He is the chair of CIE, the Center of Industrial Electronics, and his activities cover the design, verification, and reliability assessment of next-generation film capacitors.\NFrancesco Iannuzzo: Prof. Francesco Iannuzzo is currently a Professor of Reliable Power Electronics at AAU Energy, Aalborg University, Denmark. His expertise is in the field of reliability prediction and testing to failure of power electronic components under both normal and abnormal operations.\NGolta Khatibi: Dr. Golta Khatibi is the chair of the Research Group on Mechanical Properties and Reliability at the Institute for Chemical Technologies and Analytics of TU Wien, Austria. She researches primarily innovative measurement- and characterization techniques for fatigue response and long-term reliability of interconnection structures for power electronic components.\NKim Albert Storbacka Schmidt: Senior Reliability Specialist Kim A. Schmidt is an experienced test and validation engineer in the field of environmental testing of electronics. His experience is gained from more than 40 years in the field with a combination of numerous of customer specific tasks and participation in public research projects. As Kim is a mechanical engineer, vibration & mechanical shock is an area with special interest for him.\NFrancesco Iannuzzo: Prof. Iannuzzo is currently a professor of reliable power electronics at AAU Energy, Aalborg University, Denmark. His expertise is in the field of reliability prediction and testing to failure of power electronic components under both normal and abnormal operations. He is the author or co-author of about 300 publications in journals and international conferences, five book chapters, and has edited a book on Modern Power Electronic Devices (2020, IET). He has given +30 technical seminars, keynotes, and invited speeches at top-tier conferences such as ISPSD, IRPS, EPE, ECCE, PCIM, and APEC, as well as serving several times as Technical Program Co-Chair (ESREF conferences), Vice Chair (ECCE conferences), and Session Chair (ECCE, APEC, and ESREF conferences). Prof. Iannuzzo has been Associate Editor for the IEEE JESTPE and for the IEEE OJ-PE. He currently serves as the chair of the IEEE IAS Power Electronic Devices and Components Committee. He was the General Chair of the ESREF conference in 2018 (400 participants), the IWIPP conference in 2022 (80 participants), and the EPE-ECCE Europe conference in 2023 (1000 participants). X-ALT-DESC;FMTTYPE=text/html: Organizer: Francesco Iannuzzo, Aalborg University (DK)
Moderator: Francesco Iannuzzo, Aalborg University (DK)
Speakers:
Kim A. Schmidt (FORCE Technology, Hoersholm, Denmark): "From measurements to accelerated testing – a case with vibration & shock"
Francesco Iannuzzo (AAU Energy, Aalborg University, Denmark): “Testing for Abnormal Conditions of Modern Power Electronic Devices”
Golta Khatibi (Institute for Chemical Technologies and Analytics, TU Wien, Austria): “Innovative testing techniques for bond-wire fatigue in power electronic components”
Thomas Ebel (University of Southern Denmark, Denmark): “Comparison of a New Characterization Technique of Electrical Properties of Radial Aluminum Electrolytic Capacitors versus Traditional Characterization Methods”
Session’s scope and topic(s):
Power Electronics is an essential technology for the green transition. This is due to the intrinsically stochastic nature of renewable energy sources as well as the need for storage of vast amounts of energy, e.g., for transportation, in the form of electricity. For this reason, the reliability of power electronic components has become crucial in the last decade. This special session addresses the state of the art and the issues of the modern testing approaches for the reliability assessment of power electronic components.
The special session (SS) is intended to bridge the gap between the testing community (TC) and the power electronic devices community (PEDC), with an expectedly obvious benefit for both of them. The SS is organized by Prof. F. Iannuzzo, Aalborg University, Denmark, who is active in PEDC, and addresses an audience primarily belonging to the TC.
The SS has the form of four speeches, i.e., 2 x 30 minutes and 2 x 15 minutes, including Q&A, where four different speakers from the PEDC present some key challenges within the testing for reliability of power electronic components.
Thomas Ebel: Prof. Thomas Ebel is currently a Professor of Advanced Capacitor Technologies at the University of Southern Denmark (SDU), Denmark. He is the chair of CIE, the Center of Industrial Electronics, and his activities cover the design, verification, and reliability assessment of next-generation film capacitors.
Francesco Iannuzzo: Prof. Francesco Iannuzzo is currently a Professor of Reliable Power Electronics at AAU Energy, Aalborg University, Denmark. His expertise is in the field of reliability prediction and testing to failure of power electronic components under both normal and abnormal operations.
Golta Khatibi: Dr. Golta Khatibi is the chair of the Research Group on Mechanical Properties and Reliability at the Institute for Chemical Technologies and Analytics of TU Wien, Austria. She researches primarily innovative measurement- and characterization techniques for fatigue response and long-term reliability of interconnection structures for power electronic components.
Kim Albert Storbacka Schmidt: Senior Reliability Specialist Kim A. Schmidt is an experienced test and validation engineer in the field of environmental testing of electronics. His experience is gained from more than 40 years in the field with a combination of numerous of customer specific tasks and participation in public research projects. As Kim is a mechanical engineer, vibration & mechanical shock is an area with special interest for him.
Francesco Iannuzzo: Prof. Iannuzzo is currently a professor of reliable power electronics at AAU Energy, Aalborg University, Denmark. His expertise is in the field of reliability prediction and testing to failure of power electronic components under both normal and abnormal operations. He is the author or co-author of about 300 publications in journals and international conferences, five book chapters, and has edited a book on Modern Power Electronic Devices (2020, IET). He has given +30 technical seminars, keynotes, and invited speeches at top-tier conferences such as ISPSD, IRPS, EPE, ECCE, PCIM, and APEC, as well as serving several times as Technical Program Co-Chair (ESREF conferences), Vice Chair (ECCE conferences), and Session Chair (ECCE, APEC, and ESREF conferences). Prof. Iannuzzo has been Associate Editor for the IEEE JESTPE and for the IEEE OJ-PE. He currently serves as the chair of the IEEE IAS Power Electronic Devices and Components Committee. He was the General Chair of the ESREF conference in 2018 (400 participants), the IWIPP conference in 2022 (80 participants), and the EPE-ECCE Europe conference in 2023 (1000 participants).
LAST-MODIFIED:20240517T100543Z SEQUENCE:5616677 LOCATION:Johan de Wittlaan 30\, 2517 JR Den Haag\, Zuid-Holland\, Netherlands GEO:52.08989950;4.28243397 X-LOCATION-DISPLAYNAME:Room Van Gogh + Monet X-ACCESS:1 X-HITS:719 X-COLOR:3366cc X-SHOW-END-TIME:1 END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Amsterdam:20240523T140000 DTEND;TZID=Europe/Amsterdam:20240523T153000 UID:CFB51E8B-6042-4516-8710-7A62CADEDF95 SUMMARY:Special Session 6 CREATED:20240313T095515Z DTSTAMP:20240313T095515Z URL:https://ets24.ewi.tudelft.nl/index.php/home/program/conference-program/special-session-6 DESCRIPTION:\NIEEE Std P3405: New Standard-under-Development for Chiplet Interconnect Test and Repair\N \N\NOrganizer: Erik Jan Marinissen, imec (BE)\NModerator: Erik Jan Marinissen, imec (BE)\NSpeekers: Adrian Evans, CEA/LIST (FR), Po-Yao Chuang, IMEC (BE), Martin Keim, Siemens Digital Industries Software (US)\NAbstract:\NFrom the Project Authorization Request (PAR) of IEEE Std P3405:“Chiplet-based designs contain dies using proprietary interconnect technology. These dies might come from multiple design groups. Inter-chiplet interconnects are dense, large in number, and prone to manufacturing defects. For cost-effective chiplet packaging, an effective and efficient mechanism to test and repair chiplet interconnects is required. The chiplet interconnect test and repair infrastructure is spread across chiplets and designed by multiple design groups, necessitating the need for a standard for chiplet interconnect test and repair.The purpose of IEEE Std P3405 is to enable interoperability of interconnect test and repair infrastructure of chiplets from multiple design groups. Chiplet-based designs involve multiple parties: Chiplet Maker(s), Packagers, and End User(s). Features supporting the test and repair of chiplet interconnects are part of individual chiplets, which are implemented by individual Chiplet Makers. These features are needed to serve the Chiplet Makers’ (pre-packaging), Packagers’, and End Users’ test and repair objectives.”\NA. Requirements for Chiplet Interconnect Repair and Analysis of Legacy Solutions\NAdrian Evans – Research Engineer (CEA/LIST, France)\NWe define the requirements for the repair of chiplet interconnects. This includes specifying the problem and proposing a nomenclature. We discuss the requirements for achieving complete and partial repair for different fault models. The opportunities for design automation will be briefly touched upon. We close with a short review of the repair approaches for two legacy die-to-die protocols (HBM2 and AIB).\NB. Chiplet Interconnect Repair Logic Description with Google’s Protocol Buffers\NPo-Yao Chuang and Erik Jan Marinissen (imec, Belgium)\NThe anticipated outcome of IEEE Std P3405 is to provide a standardized description of repair logic within a die. This standardized representation holds the potential to facilitate the development of automation in design verification, specification-driven implementation, and the alignment of repair capabilities across dies. Our suggestion is to construct the Repair-Logic Language using Google’s Protocol Buffers (PB). PB segregates the language definition (which should be standardized) from the language itself and offers support for tool developers across various programming languages. We use the repair logic of UCIe as an illustrative example for a PB-based description language.\NC. How IEEE Std P3405 Enables EDA Interoperability\NMartin Keim – Senior Engineering Director (Siemens EDA, USA)\NOne key goal of (test) standards is enabling interoperability. For IEEE Std P3405 we must resolve the challenge that one chiplet may be built through design and design-for-test tools from one vendor, while another chiplet of the same 3D product may be formed through design and design-for-test tools from a different vendor. Both chiplets claim compatibility with IEEE Std P3405. The rightful expectation of the user is then that these chiplets work in a plug-and-play fashion with respect to design and design-for-test functionality. At the core of the resolution of this challenge lies the tool-agnostic exchange of information about the chiplet interconnect. This set of information may include the number, name, type, and grouping of interconnects, as well as their repair schema. This information may be used in multiple ways. Firstly, guiding the design-for-test implementation, and secondly to enable interconnect test and repair execution between the chiplets, all without the standard demanding a particular hardware implementation. Further, such information must enable the tooling to validate that a standard-compliant implementation in one chiplet is compatible with a standard-compliant implementation of the other chiplet. Lastly, parts of IEEE Std P3405 may cover aspects of diagnostics, like the inclusion of layout data like the XY coordinates of TSVs. In this talk, we discuss in more detail the need for each such set of data, as far as the IEEE P3405 working group understands the problem.\NBiographies of the Speakers\NAdrian Evans is a researcher at CEA/LIST. He obtained his PhD from Université Grenoble Alpes, focusing on modeling of radiation effects in complex ASICs. He worked for fifteen years on the design of complex ASICs for network routers and has extensive experience in soft errors and reliability. His current research interests are centered around HPC applications, including architectures which exploit chiplet technology.\NPo-Yao Chuang is a researcher at IMEC in Leuven, Belgium. As PhD student of the National Tsing-Hua University in Hsinchu, Taiwan, he started at IMEC in 2022, initially as an internship student. Previously, he has worked at TSMC and MediaTek in Hsinchu, Taiwan. His current research focuses on interconnect test and repair of 3D-ICs, including DfT designs and test patern generation.\NMartin Keim joined the Tessent product group of Mentor Graphics in 2001, now part of Siemens Digital Industries Software, where he is Senior Engineering Director responsible for the Memory Testing, Built-In Self-Test Diagnosis products, IJTAG infrastructure, as well as multi-die testing. For several years, Dr. Keim has worked on the organizing commitee of the International Symposium for Testing and Failure Analysis (ISTFA), for which he was General Chair in 2016. He is a past member of the IEEE 1687-2014 working group, General Chair of the current IEEE P1687 Refresh working group, and member of the working groups of UCIe, IEEE P1687.1, P1838a, and P3405. X-ALT-DESC;FMTTYPE=text/html: Organizer: Erik Jan Marinissen, imec (BE)
Moderator: Erik Jan Marinissen, imec (BE)
Speekers: Adrian Evans, CEA/LIST (FR), Po-Yao Chuang, IMEC (BE), Martin Keim, Siemens Digital Industries Software (US)
From the Project Authorization Request (PAR) of IEEE Std P3405:
“Chiplet-based designs contain dies using proprietary interconnect technology. These dies might come from multiple design groups. Inter-chiplet interconnects are dense, large in number, and prone to manufacturing defects. For cost-effective chiplet packaging, an effective and efficient mechanism to test and repair chiplet interconnects is required. The chiplet interconnect test and repair infrastructure is spread across chiplets and designed by multiple design groups, necessitating the need for a standard for chiplet interconnect test and repair.
The purpose of IEEE Std P3405 is to enable interoperability of interconnect test and repair infrastructure of chiplets from multiple design groups. Chiplet-based designs involve multiple parties: Chiplet Maker(s), Packagers, and End User(s). Features supporting the test and repair of chiplet interconnects are part of individual chiplets, which are implemented by individual Chiplet Makers. These features are needed to serve the Chiplet Makers’ (pre-packaging), Packagers’, and End Users’ test and repair objectives.”
Adrian Evans – Research Engineer (CEA/LIST, France)
We define the requirements for the repair of chiplet interconnects. This includes specifying the problem and proposing a nomenclature. We discuss the requirements for achieving complete and partial repair for different fault models. The opportunities for design automation will be briefly touched upon. We close with a short review of the repair approaches for two legacy die-to-die protocols (HBM2 and AIB).
Po-Yao Chuang and Erik Jan Marinissen (imec, Belgium)
The anticipated outcome of IEEE Std P3405 is to provide a standardized description of repair logic within a die. This standardized representation holds the potential to facilitate the development of automation in design verification, specification-driven implementation, and the alignment of repair capabilities across dies. Our suggestion is to construct the Repair-Logic Language using Google’s Protocol Buffers (PB). PB segregates the language definition (which should be standardized) from the language itself and offers support for tool developers across various programming languages. We use the repair logic of UCIe as an illustrative example for a PB-based description language.
Martin Keim – Senior Engineering Director (Siemens EDA, USA)
One key goal of (test) standards is enabling interoperability. For IEEE Std P3405 we must resolve the challenge that one chiplet may be built through design and design-for-test tools from one vendor, while another chiplet of the same 3D product may be formed through design and design-for-test tools from a different vendor. Both chiplets claim compatibility with IEEE Std P3405. The rightful expectation of the user is then that these chiplets work in a plug-and-play fashion with respect to design and design-for-test functionality. At the core of the resolution of this challenge lies the tool-agnostic exchange of information about the chiplet interconnect. This set of information may include the number, name, type, and grouping of interconnects, as well as their repair schema. This information may be used in multiple ways. Firstly, guiding the design-for-test implementation, and secondly to enable interconnect test and repair execution between the chiplets, all without the standard demanding a particular hardware implementation. Further, such information must enable the tooling to validate that a standard-compliant implementation in one chiplet is compatible with a standard-compliant implementation of the other chiplet. Lastly, parts of IEEE Std P3405 may cover aspects of diagnostics, like the inclusion of layout data like the XY coordinates of TSVs. In this talk, we discuss in more detail the need for each such set of data, as far as the IEEE P3405 working group understands the problem.
Adrian Evans is a researcher at CEA/LIST. He obtained his PhD from Université Grenoble Alpes, focusing on modeling of radiation effects in complex ASICs. He worked for fifteen years on the design of complex ASICs for network routers and has extensive experience in soft errors and reliability. His current research interests are centered around HPC applications, including architectures which exploit chiplet technology.
Po-Yao Chuang is a researcher at IMEC in Leuven, Belgium. As PhD student of the National Tsing-Hua University in Hsinchu, Taiwan, he started at IMEC in 2022, initially as an internship student. Previously, he has worked at TSMC and MediaTek in Hsinchu, Taiwan. His current research focuses on interconnect test and repair of 3D-ICs, including DfT designs and test patern generation.
Martin Keim joined the Tessent product group of Mentor Graphics in 2001, now part of Siemens Digital Industries Software, where he is Senior Engineering Director responsible for the Memory Testing, Built-In Self-Test Diagnosis products, IJTAG infrastructure, as well as multi-die testing. For several years, Dr. Keim has worked on the organizing commitee of the International Symposium for Testing and Failure Analysis (ISTFA), for which he was General Chair in 2016. He is a past member of the IEEE 1687-2014 working group, General Chair of the current IEEE P1687 Refresh working group, and member of the working groups of UCIe, IEEE P1687.1, P1838a, and P3405.
LAST-MODIFIED:20240523T114030Z SEQUENCE:6140715 LOCATION:Johan de Wittlaan 30\, 2517 JR Den Haag\, Zuid-Holland\, Netherlands GEO:52.08989950;4.28243397 X-LOCATION-DISPLAYNAME:Room Gaugain + Dali X-ACCESS:1 X-HITS:768 X-COLOR:3366cc X-SHOW-END-TIME:1 END:VEVENT END:VCALENDAR