BEGIN:VCALENDAR VERSION:2.0 PRODID:DPCALENDAR CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:Europe/Amsterdam BEGIN:STANDARD DTSTART:20251026T010000 TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET END:STANDARD BEGIN:STANDARD DTSTART:20261025T010000 TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET END:STANDARD BEGIN:DAYLIGHT DTSTART:20260329T010000 TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST END:DAYLIGHT END:VTIMEZONE X-WR-TIMEZONE:Europe/Amsterdam BEGIN:VEVENT DTSTART;TZID=Europe/Amsterdam:20240521T093000 DTEND;TZID=Europe/Amsterdam:20240521T101500 UID:74E3842C-7530-4D97-847B-2B7CBA76885E SUMMARY:Keynote 1 CREATED:20230509T133518Z DTSTAMP:20230509T133518Z URL:https://ets24.ewi.tudelft.nl/index.php/home/program/conference-program/test-keynote DESCRIPTION:\N \N \N Moderator:\N \N Maria K. Michael\N \N\N\N \N \N Affiliation:\N \N University of Cyprus (CY)\N \N\N\N \N \N Silent Data Corruption Errors in VLSI Circuits: Implications, Challenges, and Opportunities\N \N \N \N \N \N \N \N \N \N \N Author:\N \N Rama Govindaraju\N \N \N \N \N \N Affiliation:\N \N Google (US)\N \N \N \N \N \N Abstract:\N \N \N \N \N VLSI chips are the foundation of our computing infrastructure, and we all rely on it to function reliably. Trust of our users and the entire industry is at stake. There is increasing evidence of reliability issues with modern VLSI chips. The defect rates are orders of magnitude higher than what has traditionally been cited. Amplifying this challenge is the point that an increasing number of these chips are silently corrupting the execution context (or SDC - silent data corruption and is inconsistent with the expectation of a failstop model). We will also discuss the challenges emerging from degradation/aging. This discussion will summarize some of the experiences at Google and a sketch of what Google has been doing to address this growing challenge. We will attempt to increase awareness of the growing challenge and also the many opportunities for research to address this problem. The goal will be to make louder the call to action that Google has been championing for the last 5 years to enable an end-to-end solution that addresses this emerging and growing challenge for the entire computing industry. This is an industry wide problem and needs everyone to contribute to enable the solution space.\N \N \N \N \N \N Biography:\N \N \N \N \N Rama is a Director of Engineering at Google where he leads the Systems Infrastructure Architecture team. Prior to that Rama was a Distinguished Engineer at IBM responsible for leading the Software Architecture at IBM's Supercomputing Lab where he led the development of 5 generations of Supercomputers. Prior to that Rama received his MS and Phd in Computer Science from Rensselaer Polytechnic Institute in New York and BE in Computer Science from BIT Mesra, Ranchi, India.\N \N \N\N X-ALT-DESC;FMTTYPE=text/html:

Moderator: Maria K. Michael

Affiliation: University of Cyprus (CY)

Silent Data Corruption Errors in VLSI Circuits: Implications, Challenges, and Opportunities

Author: Rama Govindaraju

Affiliation: Google (US)

VLSI chips are the foundation of our computing infrastructure, and we all rely on it to function reliably. Trust of our users and the entire industry is at stake. There is increasing evidence of reliability issues with modern VLSI chips. The defect rates are orders of magnitude higher than what has traditionally been cited. Amplifying this challenge is the point that an increasing number of these chips are silently corrupting the execution context (or SDC - silent data corruption and is inconsistent with the expectation of a failstop model). We will also discuss the challenges emerging from degradation/aging. This discussion will summarize some of the experiences at Google and a sketch of what Google has been doing to address this growing challenge. We will attempt to increase awareness of the growing challenge and also the many opportunities for research to address this problem. The goal will be to make louder the call to action that Google has been championing for the last 5 years to enable an end-to-end solution that addresses this emerging and growing challenge for the entire computing industry. This is an industry wide problem and needs everyone to contribute to enable the solution space.

Rama is a Director of Engineering at Google where he leads the Systems Infrastructure Architecture team. Prior to that Rama was a Distinguished Engineer at IBM responsible for leading the Software Architecture at IBM's Supercomputing Lab where he led the development of 5 generations of Supercomputers. Prior to that Rama received his MS and Phd in Computer Science from Rensselaer Polytechnic Institute in New York and BE in Computer Science from BIT Mesra, Ranchi, India.

LAST-MODIFIED:20240325T151327Z SEQUENCE:27740289 LOCATION:Johan de Wittlaan 30\, 2517 JR Den Haag\, Zuid-Holland\, Netherlands GEO:52.08989950;4.28243397 X-LOCATION-DISPLAYNAME:Room A1 X-ACCESS:1 X-HITS:597 X-COLOR:5e4fa2 X-SHOW-END-TIME:1 END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Amsterdam:20240522T083000 DTEND;TZID=Europe/Amsterdam:20240522T091500 UID:479C0A93-8CF0-4E21-B3FC-C56F7479CA97 SUMMARY:Keynote 2 CREATED:20230509T133518Z DTSTAMP:20230509T133518Z URL:https://ets24.ewi.tudelft.nl/index.php/home/program/conference-program/test-keynote-2 DESCRIPTION:\N \N \N Moderator:\N \N Said Hamdioui\N \N\N\N \N \N Affiliation:\N \N Delft University of Technology (NL)\N \N\N\N \N \N Sustainability and the Outlook of Semiconductor Industry\N \N \N \N \N \N \N \N \N \N \N Author:\N \N Cheng-Wen Wu\N \N \N \N \N \N Affiliation:\N \N Southern Taiwan University of Science and Technology (TW)\N \N \N \N \N \N Abstract:\N \N \N \N \N The environmental sustainability and global warming issues caused by the excessive and inappropriate consumption of the earth's resources by human beings have led to the goal of net-zero carbon emissions, which have been agreed by most countries in the world. The trends of electric vehicles, green energy, smart microgrid, etc., will change many industries in the future, including the semiconductor industry. In this talk, I will try to discuss the future development of the semiconductor industry that the ETS attendees may be concerned about from different perspectives, including quality and reliability of the products and systems.\N \N \N \N \N \N Biography:\N \N \N \N \N Cheng-Wen Wu is the President of the Southern Taiwan University of Science and Technology. He received the BSEE degree from National Taiwan University, Taipei, Taiwan, in 1981, and the MS and PhD degrees in ECE from the University of California, Santa Barbara (UCSB), in 1985 and 1987, respectively. He joined the Department of EE, National Tsing Hua University (NTHU), Hsinchu, Taiwan in March 1988, and retired on Feb. 1, 2023. He was jointly appointed by ITRI as the General Director of the SOC Technology Center from 2007 to 2009, the Vice President and General Director of the Information and Communications Labs from 2010 to 2014, the Senior Vice President and General Director of ITRI's Southern Campus from 2020 to 2023. At NTHU, he had served as the Chair of EE Department, Director of IC Design Technology Center, Dean of the College of EECS, and Senior Vice President for Research. He also had served as the Chair of the IC Design Committee, Taiwan Semiconductor Industry Association (TSIA), and was on the board of Taiwan IC Design Society (TICD). Dr. Wu is an Editor for the Jour. Electronic Testing: Theory and Applications (JETTA). He was the Editor-in-Chief for the Int. Jour. Electrical Engineering (IJEE), an Editor or Associate Editor for IEEE Design and Test of Computers, IEEE Transactions on Computers, and IEEE Transactions on CAD. His research interests include design and test of VLSI circuits and systems, and semiconductor memory test and repair. He is a life member of the CIEE, a life member of Taiwan IC Design Society, a Fellow of the ROC Technology Management Society, and a Fellow of the IEEE.\N \N \N\N X-ALT-DESC;FMTTYPE=text/html:

Moderator: Said Hamdioui

Affiliation: Delft University of Technology (NL)

Sustainability and the Outlook of Semiconductor Industry

Author: Cheng-Wen Wu

Affiliation: Southern Taiwan University of Science and Technology (TW)

The environmental sustainability and global warming issues caused by the excessive and inappropriate consumption of the earth's resources by human beings have led to the goal of net-zero carbon emissions, which have been agreed by most countries in the world. The trends of electric vehicles, green energy, smart microgrid, etc., will change many industries in the future, including the semiconductor industry. In this talk, I will try to discuss the future development of the semiconductor industry that the ETS attendees may be concerned about from different perspectives, including quality and reliability of the products and systems.

Cheng-Wen Wu is the President of the Southern Taiwan University of Science and Technology. He received the BSEE degree from National Taiwan University, Taipei, Taiwan, in 1981, and the MS and PhD degrees in ECE from the University of California, Santa Barbara (UCSB), in 1985 and 1987, respectively. He joined the Department of EE, National Tsing Hua University (NTHU), Hsinchu, Taiwan in March 1988, and retired on Feb. 1, 2023. He was jointly appointed by ITRI as the General Director of the SOC Technology Center from 2007 to 2009, the Vice President and General Director of the Information and Communications Labs from 2010 to 2014, the Senior Vice President and General Director of ITRI's Southern Campus from 2020 to 2023. At NTHU, he had served as the Chair of EE Department, Director of IC Design Technology Center, Dean of the College of EECS, and Senior Vice President for Research. He also had served as the Chair of the IC Design Committee, Taiwan Semiconductor Industry Association (TSIA), and was on the board of Taiwan IC Design Society (TICD). Dr. Wu is an Editor for the Jour. Electronic Testing: Theory and Applications (JETTA). He was the Editor-in-Chief for the Int. Jour. Electrical Engineering (IJEE), an Editor or Associate Editor for IEEE Design and Test of Computers, IEEE Transactions on Computers, and IEEE Transactions on CAD. His research interests include design and test of VLSI circuits and systems, and semiconductor memory test and repair. He is a life member of the CIEE, a life member of Taiwan IC Design Society, a Fellow of the ROC Technology Management Society, and a Fellow of the IEEE.

LAST-MODIFIED:20240325T152824Z SEQUENCE:27741186 LOCATION:Johan de Wittlaan 30\, 2517 JR Den Haag\, Zuid-Holland\, Netherlands GEO:52.08989950;4.28243397 X-LOCATION-DISPLAYNAME:Room A1 X-ACCESS:1 X-HITS:475 X-COLOR:5e4fa2 X-SHOW-END-TIME:1 END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Amsterdam:20240523T083000 DTEND;TZID=Europe/Amsterdam:20240523T091500 UID:454B040A-D2D7-45EB-A585-B0733B098387 SUMMARY:Keynote 3 CREATED:20240312T142512Z DTSTAMP:20240312T142512Z URL:https://ets24.ewi.tudelft.nl/index.php/home/program/conference-program/keynote-3 DESCRIPTION:\N \N \N Moderator:\N \N Mottaqiallah Taouil\N \N\N\N \N \N Affiliation:\N \N Delft University of Technology (NL)\N \N\N\N \N \N It is All About Trust: The Road to Autonomous Driving Will Connect Test, Reliability and Safety\N \N \N \N \N \N \N \N \N \N \N Author:\N \N Juergen Alt\N \N \N \N \N \N Affiliation:\N \N Infineon Technologies (DE)\N \N \N \N \N \N Abstract:\N \N \N \N \N At some point in the future, the majority of vehicles will be autonomous. When exactly that time will be, depends not only on technical availability but also on social acceptance. Confidence in such a technical system plays an essential, if not decisive, role. Already today, automotive semiconductors have high safety requirements as well as stricter quality and reliability targets than semiconductors supplied for consumer markets. This presentation will shed light on the challenges on the hardware side in the realization of semiconductor components for autonomous vehicles. The requirements on safety and reliability for the car of the future will increase. The measures already used today during manufacturing test, for Design-for-Test and for safety enablement need to be supplemented or replaced.\N \N \N \N \N \N Biography:\N \N \N \N \N Juergen Alt is Senior Principal Engineer at Infineon. Within Infineon’s architecture group for Automotive Microcontrollers, he is responsible for test concept and Design-for-Test architecture of next generation microcontroller platform. He is in business for 25+ years working on Design & Test, Electronic Design Automation and reliability topics for Intel and Infineon. He contributed to various university and industry collaboration projects. At Friedrich-Alexander University Erlangen, Germany he is lecturer for DfT courses, and he contributed to multiple conferences by regular presentations. Juergen is based in Munich, Germany and has diploma and doctoral degrees in electrical engineering both from University of Hannover, Germany.\N \N \N\N X-ALT-DESC;FMTTYPE=text/html:

Moderator: Mottaqiallah Taouil

Affiliation: Delft University of Technology (NL)

It is All About Trust: The Road to Autonomous Driving Will Connect Test, Reliability and Safety

Author: Juergen Alt

Affiliation: Infineon Technologies (DE)

At some point in the future, the majority of vehicles will be autonomous. When exactly that time will be, depends not only on technical availability but also on social acceptance. Confidence in such a technical system plays an essential, if not decisive, role. Already today, automotive semiconductors have high safety requirements as well as stricter quality and reliability targets than semiconductors supplied for consumer markets. This presentation will shed light on the challenges on the hardware side in the realization of semiconductor components for autonomous vehicles. The requirements on safety and reliability for the car of the future will increase. The measures already used today during manufacturing test, for Design-for-Test and for safety enablement need to be supplemented or replaced.

Juergen Alt is Senior Principal Engineer at Infineon. Within Infineon’s architecture group for Automotive Microcontrollers, he is responsible for test concept and Design-for-Test architecture of next generation microcontroller platform. He is in business for 25+ years working on Design & Test, Electronic Design Automation and reliability topics for Intel and Infineon. He contributed to various university and industry collaboration projects. At Friedrich-Alexander University Erlangen, Germany he is lecturer for DfT courses, and he contributed to multiple conferences by regular presentations. Juergen is based in Munich, Germany and has diploma and doctoral degrees in electrical engineering both from University of Hannover, Germany.

LAST-MODIFIED:20240402T094336Z SEQUENCE:1797504 LOCATION:Johan de Wittlaan 30\, 2517 JR Den Haag\, Zuid-Holland\, Netherlands GEO:52.08989950;4.28243397 X-LOCATION-DISPLAYNAME:Room A1 X-ACCESS:1 X-HITS:445 X-COLOR:5e4fa2 X-SHOW-END-TIME:1 END:VEVENT END:VCALENDAR