BEGIN:VCALENDAR VERSION:2.0 PRODID:DPCALENDAR CALSCALE:GREGORIAN BEGIN:VTIMEZONE TZID:Europe/Amsterdam BEGIN:STANDARD DTSTART:20251026T010000 TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET END:STANDARD BEGIN:STANDARD DTSTART:20261025T010000 TZOFFSETFROM:+0200 TZOFFSETTO:+0100 TZNAME:CET END:STANDARD BEGIN:DAYLIGHT DTSTART:20260329T010000 TZOFFSETFROM:+0100 TZOFFSETTO:+0200 TZNAME:CEST END:DAYLIGHT END:VTIMEZONE X-WR-TIMEZONE:Europe/Amsterdam BEGIN:VEVENT DTSTART;TZID=Europe/Amsterdam:20240521T110000 DTEND;TZID=Europe/Amsterdam:20240521T123000 UID:D0552A1C-15B8-4090-85CF-8DC91C6DD9AB SUMMARY:​​​​Regular Session 1 CREATED:20240306T145445Z DTSTAMP:20240306T145445Z URL:https://ets24.ewi.tudelft.nl/index.php/home/program/conference-program/regular-session-1 DESCRIPTION:\N \N \N Moderators:\N \N Jaan Raik\N \N 1\N \N , Stephan Eggersglüß\N \N 2\N \N \N\N\N \N \N Affiliations:\N \N \N 1\N \N Tallinn University of Technology (EE),\N \N 2\N \N Siemens EDA (DE)\N \N\N\N \N \N Faulty Function Extraction for Defective Circuits\N \N \N \N \N \N \N \N \N \N \N Authors:\N \N Chris Nigh\N \N 1\N \N , Ruben Purdy\N \N 1\N \N , Wei Li\N \N 1\N \N , Subhasish Mitra\N \N 2\N \N , R.D. Blanton\N \N 1\N \N \N \N \N \N \N Affiliations:\N \N \N 1\N \N Carnegie Mellon University (US),\N \N 2\N \N Stanford University (US)\N \N \N \N \N \N Abstract:\N \N \N \N \N It is well known that understanding the behavior of silicon failures is an essential step in yield learning. It is also becoming more important for producing high quality silicon due to the increasing number of defects detected fortuitously. In order to meet this need, a new approach for extracting the precise faulty function from defective logic circuits is described. The approach is applied to nearly a 1,000 14nm failures and one use case of the results on improving ATPG is discussed.\N \N \N \N \N \N Biography:\N \N \N \N \N Shawn Blanton is a professor in the Electrical and Computer Engineering Department at Carnegie Mellon University. In 1995, he received his Ph.D. in Electrical Engineering and Computer Science from the University of Michigan, Ann Arbor. His research interests include various aspects of integrated system tests, testable design, and test methodology development.\N \N \N \N \N \N Time and Space Optimized Storage-based BIST under Multiple Voltages and Variations\N \N \N \N \N \N \N \N \N \N \N Authors:\N \N Hanieh Jafarzadeh\N \N 1\N \N , Florian Klemme\N \N 1\N \N , Hussam Amrouch\N \N 1, 3\N \N , Sybille Hellebrand\N \N 2\N \N , Hans-Joachim Wunderlich\N \N 1\N \N \N \N \N \N \N Affiliations:\N \N \N 1\N \N University of Stuttgart (DE),\N \N 2\N \N Paderborn University (DE),\N \N 3\N \N Technical University of Munich (DE)\N \N \N \N \N \N Abstract:\N \N \N \N \N Logic Built-In Self-Test (LBIST) with stored de- terministic patterns is supported by the major CAD vendors and is gaining increasing attention, especially for safety-critical applications such as automotive. It is used for both manufacturing and periodic in-field testing. An unresolved challenge so far stems from the inevitable process variations. This paper presents the first approach for storage-based BIST addressing delay faults under process variations and multiple voltages. A unified solution for pattern generation, test set compaction and BIST hardware is presented that is compatible with commercial schemes. The solution significantly outperforms traditional N-detect for tran- sition faults in terms of test set size, test application time and fault efficiency.\N \N \N \N \N \N Biography:\N \N \N \N \N Hanieh Jafarzadeh graduated with a Bachelor's in Computer Hardware Engineering at 2016 and a Master's in Computer Architecture at 2019 from Shahid Beheshti University, Tehran.. Since Feb 2021, she's with Prof. Wunderlich's group at university of Stuttgart, researching health state monitoring with the main focus on automatic pattern generation under PVT variations.\N \N \N \N \N \N Test Compression for Neuromorphic Chips\N \N \N \N \N \N \N \N \N \N \N Authors:\N \N Xin-Ping Chen\N \N 1\N \N , Hsu-Yu Huang\N \N 1\N \N , Chu-Yun Hsiao\N \N 1\N \N , Jennifer Shueh-Inn Hu\N \N 2\N \N , James Chien-Mo Li\N \N 1\N \N \N \N \N \N \N Affiliations:\N \N \N 1\N \N National Taiwan University (TW),\N \N 2\N \N Ming Chuan University (TW)\N \N \N \N \N \N Abstract:\N \N \N \N \N We propose test compression techniques to reduce the test time (test configurations and test length) for neuromorphic chips. Our test compression techniques include Dynamic Test Compression (DTC) and Static Test Compression (STC). DTC generates test configurations with machine learning. STC reduces test length under the constraint of the significance level in Two-sample Hotelling’s T-square Test. Experiments on two neuromorphic architectures show that our proposed techniques can reduce the total test configurations by 90.44% and the total test length by 93.47%, respectively. Our run time is more than 10x faster than the previous method. The proposed techniques are independent of neuromorphic chips’ applications.\N \N \N \N \N \N Biography:\N \N \N \N \N Xin-Ping Chen received a B.S. degree in electrical engineering from National Taiwan University (NTU), Taipei, Taiwan, in 2021, followed by an M.S. degree in electronics engineering from the same institution in 2023. His research includes test generation and test compression for neuromorphic chips.\N \N \N \N \N\N X-ALT-DESC;FMTTYPE=text/html:

Moderators: Jaan Raik 1 , Stephan Eggersglüß 2

Affiliations: 1 Tallinn University of Technology (EE), 2 Siemens EDA (DE)

Faulty Function Extraction for Defective Circuits

Authors: Chris Nigh 1 , Ruben Purdy 1 , Wei Li 1 , Subhasish Mitra 2 , R.D. Blanton 1

Affiliations: 1 Carnegie Mellon University (US), 2 Stanford University (US)

It is well known that understanding the behavior of silicon failures is an essential step in yield learning. It is also becoming more important for producing high quality silicon due to the increasing number of defects detected fortuitously. In order to meet this need, a new approach for extracting the precise faulty function from defective logic circuits is described. The approach is applied to nearly a 1,000 14nm failures and one use case of the results on improving ATPG is discussed.

Shawn Blanton is a professor in the Electrical and Computer Engineering Department at Carnegie Mellon University. In 1995, he received his Ph.D. in Electrical Engineering and Computer Science from the University of Michigan, Ann Arbor. His research interests include various aspects of integrated system tests, testable design, and test methodology development.

Time and Space Optimized Storage-based BIST under Multiple Voltages and Variations

Authors: Hanieh Jafarzadeh 1 , Florian Klemme 1 , Hussam Amrouch 1, 3 , Sybille Hellebrand 2 , Hans-Joachim Wunderlich 1

Affiliations: 1 University of Stuttgart (DE), 2 Paderborn University (DE), 3 Technical University of Munich (DE)

Logic Built-In Self-Test (LBIST) with stored de- terministic patterns is supported by the major CAD vendors and is gaining increasing attention, especially for safety-critical applications such as automotive. It is used for both manufacturing and periodic in-field testing. An unresolved challenge so far stems from the inevitable process variations. This paper presents the first approach for storage-based BIST addressing delay faults under process variations and multiple voltages. A unified solution for pattern generation, test set compaction and BIST hardware is presented that is compatible with commercial schemes. The solution significantly outperforms traditional N-detect for tran- sition faults in terms of test set size, test application time and fault efficiency.

Hanieh Jafarzadeh graduated with a Bachelor's in Computer Hardware Engineering at 2016 and a Master's in Computer Architecture at 2019 from Shahid Beheshti University, Tehran.. Since Feb 2021, she's with Prof. Wunderlich's group at university of Stuttgart, researching health state monitoring with the main focus on automatic pattern generation under PVT variations.

Test Compression for Neuromorphic Chips

Authors: Xin-Ping Chen 1 , Hsu-Yu Huang 1 , Chu-Yun Hsiao 1 , Jennifer Shueh-Inn Hu 2 , James Chien-Mo Li 1

Affiliations: 1 National Taiwan University (TW), 2 Ming Chuan University (TW)

We propose test compression techniques to reduce the test time (test configurations and test length) for neuromorphic chips. Our test compression techniques include Dynamic Test Compression (DTC) and Static Test Compression (STC). DTC generates test configurations with machine learning. STC reduces test length under the constraint of the significance level in Two-sample Hotelling’s T-square Test. Experiments on two neuromorphic architectures show that our proposed techniques can reduce the total test configurations by 90.44% and the total test length by 93.47%, respectively. Our run time is more than 10x faster than the previous method. The proposed techniques are independent of neuromorphic chips’ applications.

Xin-Ping Chen received a B.S. degree in electrical engineering from National Taiwan University (NTU), Taipei, Taiwan, in 2021, followed by an M.S. degree in electronics engineering from the same institution in 2023. His research includes test generation and test compression for neuromorphic chips.

LAST-MODIFIED:20240327T164537Z SEQUENCE:1821052 LOCATION:Johan de Wittlaan 30\, 2517 JR Den Haag\, Zuid-Holland\, Netherlands GEO:52.08989950;4.28243397 X-LOCATION-DISPLAYNAME:Room A1 X-ACCESS:1 X-HITS:848 X-COLOR:66c2a5 X-SHOW-END-TIME:1 END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Amsterdam:20240521T140000 DTEND;TZID=Europe/Amsterdam:20240521T153000 UID:0C8D3DD6-A99E-458E-9FA7-AC6597B9F685 SUMMARY:​​​Regular Session 2 CREATED:20240306T145445Z DTSTAMP:20240306T145445Z URL:https://ets24.ewi.tudelft.nl/index.php/home/program/conference-program/new-event DESCRIPTION:\N \N \N Moderators:\N \N Ioana Vatajelu\N \N 1\N \N , Ernesto Sanchez\N \N 2\N \N \N\N\N \N \N Affiliations:\N \N \N 1\N \N TIMA - CNRS (FR),\N \N 2\N \N Politecnico di Torino (IT)\N \N\N\N \N \N Detection of Stealthy Bitstreams in Cloud FPGAs using Graph Convolutional Networks\N \N \N \N \N \N \N \N \N \N \N Authors:\N \N Jayeeta Chaudhuri, Krishnendu Chakrabarty\N \N \N \N \N \N Affiliation:\N \N Arizona State University (US)\N \N \N \N \N \N Abstract:\N \N \N \N \N FPGAs are frequently utilized in cloud computing environments for high performance computing and neural network accelerators. Furthermore, multi-tenancy allows multiple users to upload customized modules on the FPGA, while maintaining logical isolation. However, attackers can take advantage of the multi-tenant environment to launch voltage-based attacks and denial-of-service (DoS). An attacker might stealthily split power-wasting ring oscillators (ROs) across multiple windows within an FPGA configuration bitstream, making it challenging for traditional detection mechanisms to identify these dispersed components as part of a larger malicious circuit. We propose a methodology to detect these malicious bitstreams by transforming individual windows within an FPGA bitstream into a graph-based representation. Leveraging this graph structure, our method employs graph convolutional networks (GCNs) in the training phase to capture malicious patterns from the bitstreams. We use the classification accuracy, true-positive rate, and false-positive rate metrics to quantify the effectiveness of our method across diverse power-wasting circuits on multiple FPGA boards.\N \N \N \N \N \N Biography:\N \N \N \N \N Krishnendu Chakrabarty received the B.Tech. degree from the Indian Institute of Technology Kharagpur, India, and the M.S.E. and Ph.D. degrees from the University of Michigan at Ann Arbor, USA. He is the Fulton Professor of Microelectronics in the School of Electrical, Computer and Energy Engineering at ASU and CTO of SWAP Hub. He is the Director of the ASU Center on Semiconductor Microelectronics, a Fellow of ACM and AAAS, and a Golden Core Member of the IEEE Computer Society.\N \N \N \N \N Best Paper Award Candidate\N \N \N \N \N \N Testing Spintronics Implemented Monte Carlo Dropout-Based Bayesian Neural Networks\N \N \N \N \N \N \N \N \N \N \N Authors:\N \N Soyed Tuhin Ahmed\N \N 1\N \N , Kamal Danouchi\N \N 2\N \N , Michael Hefenbrock\N \N 3\N \N , Guillaume Prenat\N \N 2\N \N , Lorena Anghel\N \N 2\N \N , Mehdi B. Tahoori\N \N 1\N \N \N \N \N \N \N Affiliations:\N \N \N 1\N \N Karlsruhe Institute of Technology (DE),\N \N 2\N \N University of Grenoble Alpes,CEA,CNRS (FR),\N \N 3\N \N RevoAI GmbH (DE)\N \N \N \N \N \N Abstract:\N \N \N \N \N Bayesian Neural Networks (BayNNs) can inherently estimate predictive uncertainty, facilitating informed decision making. Dropout-based BayNNs are increasingly implemented in Spintronics-based computation-in-memory architectures for resource-constrained yet high-performance safety-critical applications. Although uncertainty estimation is important, the reliability of Dropout generation and BayNN computation is equally important for target applications but is overlooked in existing works. However, testing BayNNs is significantly more challenging compared to conventional NNs, due to their stochastic nature. In this paper, we present for the first time the model of the non-idealities of the Spintronics-based Dropout module and analyze their impact on uncertainty estimates and accuracy. Furthermore, we propose a testing framework based on repeatability ranking for Dropout-based BayNN with up to 100% fault coverage while using only 0.2% of training data as test vectors.\N \N \N \N \N \N Biography:\N \N \N \N \N Soyed is a 4th-year PhD student at Karlsruhe Institute of Technology with Prof. Mehdi Tahoori. He received his master’s degree with merit from Technical University of Munich with Prof. Ulf Schlichtmann and his bachelor’s degree from American International University Bangladesh with Summa Cum Laude and University Gold Medal in 2016. His PhD research, has won three best paper nominations at IEEE VTS, DATE, and NanoArch conferences and won the best paper award from IEEE JETCAS Journal.\N \N \N \N \N \N On-chip Built-In Self-Calibration of Thermal Variations for Mixed-Signal In-Memory Computing\N \N \N \N \N \N \N \N \N \N \N Authors:\N \N Gaurav Singh\N \N 1\N \N , Omar Numan\N \N 1\N \N , Dipesh Monga\N \N 1\N \N , Martin Andraud\N \N 1, 2\N \N , Kari Halonen\N \N 1\N \N \N \N \N \N \N Affiliations:\N \N \N 1\N \N Aalto University (FI),\N \N 2\N \N UC Louvain (BE)\N \N \N \N \N \N Abstract:\N \N \N \N \N In-memory computing (IMC) accelerators have become a pivotal architecture for enhancing AI algorithm computations, particularly critical for embedding deep neural networks (DNNs) in edge devices. The efficiency of these systems is paramount, yet IMC cores are prone to fluctuations due to process, temperature, and voltage variations, which can detrimentally impact DNN accuracy. This research introduces an innovative Built-In Self-Calibration (BISC) methodology, specifically designed to compensate for temperature-induced variations in mixed-signal IMC cores. The methodology enables real-time, on-chip adjustment of DNN weights during computation within the IMC core without modifying the computation path. The proposed approach, implemented on a silicon prototype, not only maintained DNN computation accuracy under substantial temperature variations but also fully compensated for almost 90% of the offset caused by these variations, without introducing any non-idealities.\N \N \N \N \N \N Biography:\N \N \N \N \N Gaurav Singh, an IEEE Student Member, earned his M.Sc. in VLSI from Amity University, India, in 2015. He is currently pursuing his Ph.D. at Aalto University, Finland, focusing on low-power SoCs for sensor data processing. His research includes microprocessors, low-power SRAM, and serial interfaces, specifically integrating RISC-V with Compute In-Memory cores to enhance AI power efficiency.\N \N \N \N \N\N X-ALT-DESC;FMTTYPE=text/html:

Moderators: Ioana Vatajelu 1 , Ernesto Sanchez 2

Affiliations: 1 TIMA - CNRS (FR), 2 Politecnico di Torino (IT)

Detection of Stealthy Bitstreams in Cloud FPGAs using Graph Convolutional Networks

Authors: Jayeeta Chaudhuri, Krishnendu Chakrabarty

Affiliation: Arizona State University (US)

FPGAs are frequently utilized in cloud computing environments for high performance computing and neural network accelerators. Furthermore, multi-tenancy allows multiple users to upload customized modules on the FPGA, while maintaining logical isolation. However, attackers can take advantage of the multi-tenant environment to launch voltage-based attacks and denial-of-service (DoS). An attacker might stealthily split power-wasting ring oscillators (ROs) across multiple windows within an FPGA configuration bitstream, making it challenging for traditional detection mechanisms to identify these dispersed components as part of a larger malicious circuit. We propose a methodology to detect these malicious bitstreams by transforming individual windows within an FPGA bitstream into a graph-based representation. Leveraging this graph structure, our method employs graph convolutional networks (GCNs) in the training phase to capture malicious patterns from the bitstreams. We use the classification accuracy, true-positive rate, and false-positive rate metrics to quantify the effectiveness of our method across diverse power-wasting circuits on multiple FPGA boards.

Krishnendu Chakrabarty received the B.Tech. degree from the Indian Institute of Technology Kharagpur, India, and the M.S.E. and Ph.D. degrees from the University of Michigan at Ann Arbor, USA. He is the Fulton Professor of Microelectronics in the School of Electrical, Computer and Energy Engineering at ASU and CTO of SWAP Hub. He is the Director of the ASU Center on Semiconductor Microelectronics, a Fellow of ACM and AAAS, and a Golden Core Member of the IEEE Computer Society.

Best Paper Award Candidate

Testing Spintronics Implemented Monte Carlo Dropout-Based Bayesian Neural Networks

Authors: Soyed Tuhin Ahmed 1 , Kamal Danouchi 2 , Michael Hefenbrock 3 , Guillaume Prenat 2 , Lorena Anghel 2 , Mehdi B. Tahoori 1

Affiliations: 1 Karlsruhe Institute of Technology (DE), 2 University of Grenoble Alpes,CEA,CNRS (FR), 3 RevoAI GmbH (DE)

Bayesian Neural Networks (BayNNs) can inherently estimate predictive uncertainty, facilitating informed decision making. Dropout-based BayNNs are increasingly implemented in Spintronics-based computation-in-memory architectures for resource-constrained yet high-performance safety-critical applications. Although uncertainty estimation is important, the reliability of Dropout generation and BayNN computation is equally important for target applications but is overlooked in existing works. However, testing BayNNs is significantly more challenging compared to conventional NNs, due to their stochastic nature. In this paper, we present for the first time the model of the non-idealities of the Spintronics-based Dropout module and analyze their impact on uncertainty estimates and accuracy. Furthermore, we propose a testing framework based on repeatability ranking for Dropout-based BayNN with up to 100% fault coverage while using only 0.2% of training data as test vectors.

Soyed is a 4th-year PhD student at Karlsruhe Institute of Technology with Prof. Mehdi Tahoori. He received his master’s degree with merit from Technical University of Munich with Prof. Ulf Schlichtmann and his bachelor’s degree from American International University Bangladesh with Summa Cum Laude and University Gold Medal in 2016. His PhD research, has won three best paper nominations at IEEE VTS, DATE, and NanoArch conferences and won the best paper award from IEEE JETCAS Journal.

On-chip Built-In Self-Calibration of Thermal Variations for Mixed-Signal In-Memory Computing

Authors: Gaurav Singh 1 , Omar Numan 1 , Dipesh Monga 1 , Martin Andraud 1, 2 , Kari Halonen 1

Affiliations: 1 Aalto University (FI), 2 UC Louvain (BE)

In-memory computing (IMC) accelerators have become a pivotal architecture for enhancing AI algorithm computations, particularly critical for embedding deep neural networks (DNNs) in edge devices. The efficiency of these systems is paramount, yet IMC cores are prone to fluctuations due to process, temperature, and voltage variations, which can detrimentally impact DNN accuracy. This research introduces an innovative Built-In Self-Calibration (BISC) methodology, specifically designed to compensate for temperature-induced variations in mixed-signal IMC cores. The methodology enables real-time, on-chip adjustment of DNN weights during computation within the IMC core without modifying the computation path. The proposed approach, implemented on a silicon prototype, not only maintained DNN computation accuracy under substantial temperature variations but also fully compensated for almost 90% of the offset caused by these variations, without introducing any non-idealities.

Gaurav Singh, an IEEE Student Member, earned his M.Sc. in VLSI from Amity University, India, in 2015. He is currently pursuing his Ph.D. at Aalto University, Finland, focusing on low-power SoCs for sensor data processing. His research includes microprocessors, low-power SRAM, and serial interfaces, specifically integrating RISC-V with Compute In-Memory cores to enhance AI power efficiency.

LAST-MODIFIED:20240325T151338Z SEQUENCE:1642733 LOCATION:Johan de Wittlaan 30\, 2517 JR Den Haag\, Zuid-Holland\, Netherlands GEO:52.08989950;4.28243397 X-LOCATION-DISPLAYNAME:Room A1 X-ACCESS:1 X-HITS:901 X-COLOR:66c2a5 X-SHOW-END-TIME:1 END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Amsterdam:20240521T161500 DTEND;TZID=Europe/Amsterdam:20240521T174500 UID:FDDA1A12-D7C7-4EF1-9F7F-7FE692C312C4 SUMMARY:​​​Regular Session 3 CREATED:20240311T160627Z DTSTAMP:20240311T160627Z URL:https://ets24.ewi.tudelft.nl/index.php/home/program/conference-program/regular-session-3 DESCRIPTION:\N \N \N Moderators:\N \N Sybille Hellebrand\N \N 1\N \N , Grzegorz Mrugalski\N \N 2\N \N \N\N\N \N \N Affiliations:\N \N \N 1\N \N Paderborn University (DE),\N \N 2\N \N Siemens EDA (PL)\N \N\N\N \N \N Test and Repair Improvements for UCIe\N \N \N \N \N \N \N \N \N \N \N Authors:\N \N Tsung-Hsuan Wang\N \N 1, 2\N \N , Po-Yao Chuang\N \N 1, 3\N \N , Francesco Lorenzelli\N \N 1, 4\N \N , Erik Jan Marinissen\N \N 1, 5\N \N \N \N \N \N \N Affiliations:\N \N \N 1\N \N IMEC (BE),\N \N 2\N \N NYCU (TW),\N \N 3\N \N NTHU (TW),\N \N 4\N \N KU Leuven (BE),\N \N 5\N \N TU Eindhoven (NL)\N \N \N \N \N \N Abstract:\N \N \N \N \N The success of chiplet-based design critically depends on standards, especially those for die-to-die interconnects. Universal Chiplet Interconnect Express (UCIe) is such a standard, showing promising potential in its field. Among other things, UCIe standardizes the micro-bump map. It incorporates several spare interconnects able to “repair” defective interconnects. We outline a very efficient, aliasing-free test generation method for all hard and weak short and open manufacturing defects on die-to-die interconnects that uses just 16 test patterns, irrespective of the number of interconnects. We also propose to improve repairability of the UCIe interconnects through reorganizations of the micro-bump map that eliminate the risk for non-repairable (‘catastrophic’) defects and minimizes the usage of spare interconnects. The micro-bump map reorganizations are not backwards compatible and hence, since UCIe is still in its early stages of actual usage, it would be best to incorporate this improvement in the standard as soon as possible.\N \N \N \N \N \N Biography:\N \N \N \N \N Scientific Director at imec in Leuven, Belgium, where he is responsible for research on test and design-for-test, covering topics as diverse as 3D-stacked ICs, silicon photonics, CMOS technology nodes below 10nm, and STT-MRAMs.\NVisiting Researcher at Eindhoven University of Technology (TU/e) in the Netherlands.\NPreviously at NXP Semiconductors and Philips Research Laboratories in Eindhoven, Nijmegen, and Sunnyvale.\NMSc and PDEng degrees from TU/e.\N \N \N \N \N Best Paper Award Candidate\N \N \N \N \N \N IEEE 1838 compliant scan encryption and integrity for 2.5/3D ICs\N \N \N \N \N \N \N \N \N \N \N Authors:\N \N Juan Suzano[0,1,2],{Antoine Chastand\N \N 1\N \N , Emanuele Valea\N \N 2\N \N , Giorgio Di Natale\N \N 3\N \N , Anthony Philippe\N \N 2\N \N , Fady Abouzeid\N \N 1\N \N , Philippe Roche\N \N 1\N \N \N \N \N \N \N Affiliations:\N \N \N 1\N \N STMicroelectronics (FR),\N \N 2\N \N University Grenoble Alpes, CEA (FR),\N \N 3\N \N University Grenoble Alpes, CNRS, Grenoble INP (FR)\N \N \N \N \N \N Abstract:\N \N \N \N \N 2.5D and 3D integrated circuits (IC) are the natural evolution of traditional 2D SoCs. 2.5D and 3D integration is the process of assembling pre-manufactured chiplets in an interposer or in a stack. This process can damage the chiplets or lead to faulty connections. Thus, the importance of post-bond test of chiplets. The IEEE Std 1838(TM)-2019 (IEEE 1838) design-for-testability (DFT) standard defines mandatory and optional structures for accessing DFT functions on the chiplet. Compliant chiplets form a DFT network that can be exploited by attackers to violate the confidentiality or integrity of the message transmitted over the serial path. In this work, we combine a message integrity verifica- tion system with a scan encryption mechanism to protect the scan chain of an IEEE 1838-compliant DFT implementation. The scan encryption prevents unauthorized actors from writing meaningful data into the scan chain. Message integrity verification makes messages from untrustworthy sources detectable. In conjunction, both security primitives protect the scan chain from malicious chiplets on the stack, scan-based attacks, and brute force attacks. The proposed solution causes less than 1% area overhead on designs composed of more than 5 million gates and less than 1% test time overhead for typical DFT implementations.\N \N \N \N \N \N Biography:\N \N \N \N \N Juan Suzano received the B.S. degree in computer engineering from the federal university of Rio Grande do Sul and the M.S. degree from CPE Lyon through the double degree program BRAFITEC, in 2022. He is currently pursuing the Ph.D. degree in micro and nano electronics with Grenoble Alpes University in partnership with STMicroelectronics and CEA Grenoble. He is invested in the research and development of security hardware solutions for chiplet-based 2.5D and 3D integrated circuits.\N \N \N \N \N \N Design-for-Test for Intermittent Faults in STT-MRAMs\N \N \N \N \N \N \N \N \N \N \N Authors:\N \N Sicong Yuan\N \N 1, 3\N \N , Mohammad Amin Yaldagard\N \N 1\N \N , Hanzhi Xun\N \N 1\N \N , Moritz Fieback\N \N 1\N \N , Erik Jan Marinissen\N \N 3\N \N , Woojin Kim\N \N 3\N \N , Siddharth Rao\N \N 3\N \N , Sebastien Couet\N \N 3\N \N , Mottaqiallah Taouil\N \N 1, 2\N \N , Said Hamdioui\N \N 1, 2\N \N \N \N \N \N \N Affiliations:\N \N \N 1\N \N TU Delft (NL),\N \N 2\N \N CognitiveIC (NL),\N \N 3\N \N IMEC (BE)\N \N \N \N \N \N Abstract:\N \N \N \N \N Guaranteeing high-quality test solutions for Spin-Transfer Torque Magnetic RAM (STT-MRAM) is a must to speed up its high-volume production. A high test quality requires maximizing the fault coverage. Detecting permanent faults is relatively simple compared to intermittent faults; the latter are faults (caused by non-environmental conditions) that appear and disappear as a function of time, and are therefore hard to detect. Testing for such faults in STT-MRAMs is even worse considering the Magnetic Tunneling Junction inherent property ‘intrinsic switching stochasticity’, which results in inevitable random write errors. This paper presents a novel Design-for-Testability (DFT) scheme for detecting intermittent faults in STT-MRAMs; it is based on monitoring the write current. The strength of the write current is inversely correlated to the write error rate; when the write current is smaller than the specification, the device is considered faulty. A reduction in the write current can be caused by any defect in the write path of the memory (e.g., interconnects and contacts). Simulation results based on industrial design show that applying DFT yields a superior coverage of intermittent faults compared to functional test methods, such as march tests.\N \N \N \N \N \N Biography:\N \N \N \N \N SicongYuan is a phd candidate in Delft University of Technology, Netherlands\N \N \N \N \N\N X-ALT-DESC;FMTTYPE=text/html:

Moderators: Sybille Hellebrand 1 , Grzegorz Mrugalski 2

Affiliations: 1 Paderborn University (DE), 2 Siemens EDA (PL)

Test and Repair Improvements for UCIe

Authors: Tsung-Hsuan Wang 1, 2 , Po-Yao Chuang 1, 3 , Francesco Lorenzelli 1, 4 , Erik Jan Marinissen 1, 5

Affiliations: 1 IMEC (BE), 2 NYCU (TW), 3 NTHU (TW), 4 KU Leuven (BE), 5 TU Eindhoven (NL)

The success of chiplet-based design critically depends on standards, especially those for die-to-die interconnects. Universal Chiplet Interconnect Express (UCIe) is such a standard, showing promising potential in its field. Among other things, UCIe standardizes the micro-bump map. It incorporates several spare interconnects able to “repair” defective interconnects. We outline a very efficient, aliasing-free test generation method for all hard and weak short and open manufacturing defects on die-to-die interconnects that uses just 16 test patterns, irrespective of the number of interconnects. We also propose to improve repairability of the UCIe interconnects through reorganizations of the micro-bump map that eliminate the risk for non-repairable (‘catastrophic’) defects and minimizes the usage of spare interconnects. The micro-bump map reorganizations are not backwards compatible and hence, since UCIe is still in its early stages of actual usage, it would be best to incorporate this improvement in the standard as soon as possible.

Scientific Director at imec in Leuven, Belgium, where he is responsible for research on test and design-for-test, covering topics as diverse as 3D-stacked ICs, silicon photonics, CMOS technology nodes below 10nm, and STT-MRAMs.Visiting Researcher at Eindhoven University of Technology (TU/e) in the Netherlands.Previously at NXP Semiconductors and Philips Research Laboratories in Eindhoven, Nijmegen, and Sunnyvale.MSc and PDEng degrees from TU/e.

Best Paper Award Candidate

IEEE 1838 compliant scan encryption and integrity for 2.5/3D ICs

Authors: Juan Suzano[0,1,2],{Antoine Chastand 1 , Emanuele Valea 2 , Giorgio Di Natale 3 , Anthony Philippe 2 , Fady Abouzeid 1 , Philippe Roche 1

Affiliations: 1 STMicroelectronics (FR), 2 University Grenoble Alpes, CEA (FR), 3 University Grenoble Alpes, CNRS, Grenoble INP (FR)

2.5D and 3D integrated circuits (IC) are the natural evolution of traditional 2D SoCs. 2.5D and 3D integration is the process of assembling pre-manufactured chiplets in an interposer or in a stack. This process can damage the chiplets or lead to faulty connections. Thus, the importance of post-bond test of chiplets. The IEEE Std 1838(TM)-2019 (IEEE 1838) design-for-testability (DFT) standard defines mandatory and optional structures for accessing DFT functions on the chiplet. Compliant chiplets form a DFT network that can be exploited by attackers to violate the confidentiality or integrity of the message transmitted over the serial path. In this work, we combine a message integrity verifica- tion system with a scan encryption mechanism to protect the scan chain of an IEEE 1838-compliant DFT implementation. The scan encryption prevents unauthorized actors from writing meaningful data into the scan chain. Message integrity verification makes messages from untrustworthy sources detectable. In conjunction, both security primitives protect the scan chain from malicious chiplets on the stack, scan-based attacks, and brute force attacks. The proposed solution causes less than 1% area overhead on designs composed of more than 5 million gates and less than 1% test time overhead for typical DFT implementations.

Juan Suzano received the B.S. degree in computer engineering from the federal university of Rio Grande do Sul and the M.S. degree from CPE Lyon through the double degree program BRAFITEC, in 2022. He is currently pursuing the Ph.D. degree in micro and nano electronics with Grenoble Alpes University in partnership with STMicroelectronics and CEA Grenoble. He is invested in the research and development of security hardware solutions for chiplet-based 2.5D and 3D integrated circuits.

Design-for-Test for Intermittent Faults in STT-MRAMs

Authors: Sicong Yuan 1, 3 , Mohammad Amin Yaldagard 1 , Hanzhi Xun 1 , Moritz Fieback 1 , Erik Jan Marinissen 3 , Woojin Kim 3 , Siddharth Rao 3 , Sebastien Couet 3 , Mottaqiallah Taouil 1, 2 , Said Hamdioui 1, 2

Affiliations: 1 TU Delft (NL), 2 CognitiveIC (NL), 3 IMEC (BE)

Guaranteeing high-quality test solutions for Spin-Transfer Torque Magnetic RAM (STT-MRAM) is a must to speed up its high-volume production. A high test quality requires maximizing the fault coverage. Detecting permanent faults is relatively simple compared to intermittent faults; the latter are faults (caused by non-environmental conditions) that appear and disappear as a function of time, and are therefore hard to detect. Testing for such faults in STT-MRAMs is even worse considering the Magnetic Tunneling Junction inherent property ‘intrinsic switching stochasticity’, which results in inevitable random write errors. This paper presents a novel Design-for-Testability (DFT) scheme for detecting intermittent faults in STT-MRAMs; it is based on monitoring the write current. The strength of the write current is inversely correlated to the write error rate; when the write current is smaller than the specification, the device is considered faulty. A reduction in the write current can be caused by any defect in the write path of the memory (e.g., interconnects and contacts). Simulation results based on industrial design show that applying DFT yields a superior coverage of intermittent faults compared to functional test methods, such as march tests.

SicongYuan is a phd candidate in Delft University of Technology, Netherlands

LAST-MODIFIED:20240325T152200Z SEQUENCE:1206933 LOCATION:Johan de Wittlaan 30\, 2517 JR Den Haag\, Zuid-Holland\, Netherlands GEO:52.08989950;4.28243397 X-LOCATION-DISPLAYNAME:Room A1 X-ACCESS:1 X-HITS:758 X-COLOR:66c2a5 X-SHOW-END-TIME:1 END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Amsterdam:20240522T091500 DTEND;TZID=Europe/Amsterdam:20240522T101500 UID:A48CDA03-6096-4A6E-BC01-6C1CEEF22EBE SUMMARY: ​​​Regular Session 4 CREATED:20240311T160816Z DTSTAMP:20240311T160816Z URL:https://ets24.ewi.tudelft.nl/index.php/home/program/conference-program/regular-session-4 DESCRIPTION:\N \N \N Moderators:\N \N Vladimir Zivkovic\N \N 1\N \N , Michele Portolan\N \N 2\N \N \N\N\N \N \N Affiliations:\N \N \N 1\N \N Siemens EDA (DK),\N \N 2\N \N Grenoble INP (FR)\N \N\N\N \N \N Characterization of Ultra-low Random Jitter Reduction Methods up to 36 GHz\N \N \N \N \N \N \N \N \N \N \N Authors:\N \N David Keezer\N \N 1\N \N , Dany Minier\N \N 2\N \N , Hongjie Li\N \N 3\N \N \N \N \N \N \N Affiliations:\N \N \N 1\N \N Eastern Institute of Technology (CN),\N \N 2\N \N Boreas Technologies (CA),\N \N 3\N \N Tianjin University (CN)\N \N \N \N \N \N Abstract:\N \N \N \N \N This paper describes methods for reducing and measuring random jitter (RJ) of clock signals in multi-GHz test instruments. The methods are based on real-time averaging of parallel/synchronized signals with uncorrelated RJ. Prior work (up to 10 GHz) is extended by experimental demonstration up to 36 GHz with RJ below 200 femtoseconds (fs). The theory of operation is reviewed and experimental results are shown for 12 and 36 GHz. A de-embedding procedure is used to separate the jitter contribution of the test instruments (jitter “floor”) from the measured values to obtain a better estimate of the actual ultra-low jitter values of the measured signals. The effects of amplitude imbalance, signal-skew, cycle-to-cycle jitter correlation, and component-added RJ are measured and analyzed.\N \N \N \N \N \N Biography:\N \N \N \N \N Dr. Keezer is a Chair professor of Information Science and Technology at the Eastern Institute of Technology in Ningbo, China. \NBefore joining EIT in 2022, he was a Professor of Electrical and Computer Engineering at Georgia Institute of Technology (for 27 years) and is currently Professor emeritus. \NHe has published over 270 peer-reviewed articles and has been an IEEE Fellow since 2010.\N \N \N \N \N \N Hierarchical Fault Simulation for Mixed-Signal Circuits Using Template Based Fault Response Modeling\N \N \N \N \N \N \N \N \N \N \N Authors:\N \N Tolga Aksoy\N \N 1\N \N , Nikhil Sagar Modala\N \N 1\N \N , Lakshmanan Balasubramanian\N \N 2\N \N , Rubin Parekhji\N \N 2\N \N , Sule Ozev\N \N 1\N \N \N \N \N \N \N Affiliations:\N \N \N 1\N \N Arizona State University (US),\N \N 2\N \N Texas Instruments (IN)\N \N \N \N \N \N Abstract:\N \N \N \N \N The objective of fault simulation is to estimate the fault coverage of a given test input. Established fault models in the analog domain are based on detailed transistor-level netlists. Existing fault simulation tools inject and analyze fault responses at this level of detail. However, extending fault simulation to large circuits, especially when digital signals and/or frequency translation is involved, can be difficult due to the nature of simulations. Designers work with models at higher abstraction levels where simulations are more efficient. The goal of this paper is to bridge the gap between available transistor-level fault simulation tools, where fault simulation can be accurate, and behavioral abstraction levels, where simulation time can be shorter. We aim to achieve this by judiciously adding various functional enhancements to individual functional blocks from a list of templates into their behavioral model until the responses at the two abstraction levels match. Transistor-level simulations are only limited to smaller functional blocks, where they are feasible, and individual fault responses are captured for behavioral simulations. Experimental results on two example circuits, a flash ADC and a PLL, show that accurate simulations can be achieved at a fraction of the simulation time.\N \N \N \N\N X-ALT-DESC;FMTTYPE=text/html:

Moderators: Vladimir Zivkovic 1 , Michele Portolan 2

Affiliations: 1 Siemens EDA (DK), 2 Grenoble INP (FR)

Characterization of Ultra-low Random Jitter Reduction Methods up to 36 GHz

Authors: David Keezer 1 , Dany Minier 2 , Hongjie Li 3

Affiliations: 1 Eastern Institute of Technology (CN), 2 Boreas Technologies (CA), 3 Tianjin University (CN)

This paper describes methods for reducing and measuring random jitter (RJ) of clock signals in multi-GHz test instruments. The methods are based on real-time averaging of parallel/synchronized signals with uncorrelated RJ. Prior work (up to 10 GHz) is extended by experimental demonstration up to 36 GHz with RJ below 200 femtoseconds (fs). The theory of operation is reviewed and experimental results are shown for 12 and 36 GHz. A de-embedding procedure is used to separate the jitter contribution of the test instruments (jitter “floor”) from the measured values to obtain a better estimate of the actual ultra-low jitter values of the measured signals. The effects of amplitude imbalance, signal-skew, cycle-to-cycle jitter correlation, and component-added RJ are measured and analyzed.

Dr. Keezer is a Chair professor of Information Science and Technology at the Eastern Institute of Technology in Ningbo, China. Before joining EIT in 2022, he was a Professor of Electrical and Computer Engineering at Georgia Institute of Technology (for 27 years) and is currently Professor emeritus. He has published over 270 peer-reviewed articles and has been an IEEE Fellow since 2010.

Hierarchical Fault Simulation for Mixed-Signal Circuits Using Template Based Fault Response Modeling

Authors: Tolga Aksoy 1 , Nikhil Sagar Modala 1 , Lakshmanan Balasubramanian 2 , Rubin Parekhji 2 , Sule Ozev 1

Affiliations: 1 Arizona State University (US), 2 Texas Instruments (IN)

The objective of fault simulation is to estimate the fault coverage of a given test input. Established fault models in the analog domain are based on detailed transistor-level netlists. Existing fault simulation tools inject and analyze fault responses at this level of detail. However, extending fault simulation to large circuits, especially when digital signals and/or frequency translation is involved, can be difficult due to the nature of simulations. Designers work with models at higher abstraction levels where simulations are more efficient. The goal of this paper is to bridge the gap between available transistor-level fault simulation tools, where fault simulation can be accurate, and behavioral abstraction levels, where simulation time can be shorter. We aim to achieve this by judiciously adding various functional enhancements to individual functional blocks from a list of templates into their behavioral model until the responses at the two abstraction levels match. Transistor-level simulations are only limited to smaller functional blocks, where they are feasible, and individual fault responses are captured for behavioral simulations. Experimental results on two example circuits, a flash ADC and a PLL, show that accurate simulations can be achieved at a fraction of the simulation time.

LAST-MODIFIED:20240520T205748Z SEQUENCE:6065372 LOCATION:Johan de Wittlaan 30\, 2517 JR Den Haag\, Zuid-Holland\, Netherlands GEO:52.08989950;4.28243397 X-LOCATION-DISPLAYNAME:Room A1 X-ACCESS:1 X-HITS:721 X-COLOR:66c2a5 X-SHOW-END-TIME:1 END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Amsterdam:20240522T110000 DTEND;TZID=Europe/Amsterdam:20240522T123000 UID:9CA027CE-8455-470B-9B3A-5DB8440C4C41 SUMMARY: ​​​Regular Session 5 CREATED:20240311T160816Z DTSTAMP:20240311T160816Z URL:https://ets24.ewi.tudelft.nl/index.php/home/program/conference-program/regular-session-5 DESCRIPTION:\N \N \N Moderators:\N \N Annachiara Ruospo\N \N 1\N \N , Zebo Peng\N \N 2\N \N \N\N\N \N \N Affiliations:\N \N \N 1\N \N Politecnico di Torino (IT),\N \N 2\N \N Linköping University (SE)\N \N\N\N \N \N Degradation Monitoring Through Software-controlled On-chip Sensors for RISC-V\N \N \N \N \N \N \N \N \N \N \N Authors:\N \N S. Maryam Ghasemi, Jonas Krautter, Tara Gheshlaghi, Sergej Meschkov, Dennis R. E. Gnad, Mehdi B. Tahoori\N \N \N \N \N \N Affiliation:\N \N Karlsruhe Institute of Technology (DE)\N \N \N \N \N \N Abstract:\N \N \N \N \N Complex systems are subject to various hardware and software defects and faults through the entire design and deployment lifecycle. Many of such defects originate at the electrical or circuit levels, but manifest as functional failures in the field. In this study, we present a methodology for embed- ding and employing software-controlled runtime variation and degradation sensors on a RISC-V SoC to enable system-level and functional testing in the field. We demonstrate the effectiveness of the entire platform through an FPGA implementation. Delay defects and path degradations are emulated by injecting artificial delay elements into the critical path of a specific instruction. We also emulate the effect of workload-induced runtime stress with tunable software-controlled power wasters. Combining various sensors, we show that transient fluctuations, which are caused by temperature or workload, can be effectively separated from persistent delay increase, which is caused by latent manufacturing defects or aging.\N \N \N \N \N \N Biography:\N \N \N \N \N Maryam received her Bachelor's and Master's degrees from the University of Tehran in the field of Electrical Engineering-Digital Systems. In September 2022, she joined the CDNC group at the Karlsruhe Institute of Technology (KIT) as a PhD student under the supervision of Professor Mehdi Tahoori. Her areas of interest include Silicon Lifecycle Management (SLM), Silent Data Corruption (SDC), RISC-V processors, FPGAs, testing, and deep learning.\N \N \N \N \N Best Paper Award Candidate\N \N \N \N \N \N Cross-Layer Reliability Analysis of NVDLA Accelerators: Exploring the Configuration Space\N \N \N \N \N \N \N \N \N \N \N Authors:\N \N Alessandro Veronesi\N \N 1\N \N , Alessandro Nazzari\N \N 2\N \N , Dario Passarello\N \N 2\N \N , Milos Krstic\N \N 1, 3\N \N , Michele Favalli\N \N 4\N \N , Luca Cassano\N \N 2\N \N , Antonio Miele\N \N 2\N \N , Davide Bertozzi\N \N 5\N \N , Cristiana Bolchini\N \N 1\N \N \N \N \N \N \N Affiliations:\N \N \N 1\N \N IHP - Microelectronics (DE),\N \N 2\N \N Politecnico di Milano (IT),\N \N 3\N \N University of Potsdam (DE),\N \N 4\N \N University degli Studi di Ferrara (IT),\N \N 5\N \N University of Manchester (UK)\N \N \N \N \N \N Abstract:\N \N \N \N \N Investigating the effects of Single Event Upset in domain-specific accelerators represents one of the key enablers to deploy Deep Neural Networks (DNNs) in mission-critical edge applications. Currently, reliability analyses related to DNNs mainly focus either on the DNNs model, at application level, or on the hardware accelerator, at architecture level. This paper presents a systematic cross-layer reliability analysis of NVIDIA Deep-Learning Accelerator, a popular family of industry-grade, open and free DNN accelerators. The goals are i) to analyze the propagation of faults from the hardware to the application level, and ii) to compare different architectural configurations. Our investigation delivers new insights into the performance-accuracy-reliability trade-off spanned by the configuration space of Deep Learning accelerators. In particular, the Failure in Time can be reduced up to 4.3x for the same DNN model accuracy and by up to 9.4x for the same performance, while accounting 6.5x inference latency and 1.1% accuracy drop, respectively.\N \N \N \N \N \N Biography:\N \N \N \N \N Graduated in March 2020 at University of Ferrara (IT), A. Veronesi is at the moment PhD student at IHP - Microelectronics (DE).\NHis research majorly focus on computer architecture, dependable AI systems, and cross-layer verification methodologies.\N \N \N \N \N \N CGAN-based Automated Fault Injection\N \N \N \N \N \N \N \N \N \N \N Authors:\N \N Troya Cagil Köylü, Cornelis Christiaan Berg, Praveen Vadnala\N \N \N \N \N \N Affiliation:\N \N Riscure B.V. (NL)\N \N \N \N \N \N Abstract:\N \N \N \N \N Fault injection is a major threat to electronic devices. Consequently, developers or independent test labs spend significant time and effort in identifying fault injection vulnerabilities. While there are proposed methods to automate fault injection vulnerability identification, their performance depend on observing many successful glitches first to generate more of them. This takes a considerable amount of time and it is common for fault injection campaigns to produce no or very few successful glitches initially. To address this issue, we propose a conditional generative adversarial network (CGAN)-based automated fault injection method. Our method finds promising regions in the parameter space even without observing successful glitches, as well as adjusts itself after observing them. Experimental results show that our method proposes at least 1.3 times more successful glitch parameters than the state of the art in both voltage and electromagnetic (EM)-based fault injection.\N \N \N \N \N \N Biography:\N \N \N \N \N Troya Koylu, born in 1992 in Turkey, completed his bachelors and masters studies in Bilkent University. In 2023, he was awarded the PhD title by the Delft University of Technology, with the thesis "Countermeasures against Fault Injection Attacks in Neural Networks and Processors". Since then, he is working in Riscure as a security analyst and researcher.\N \N \N \N \N\N X-ALT-DESC;FMTTYPE=text/html:

Moderators: Annachiara Ruospo 1 , Zebo Peng 2

Affiliations: 1 Politecnico di Torino (IT), 2 Linköping University (SE)

Degradation Monitoring Through Software-controlled On-chip Sensors for RISC-V

Authors: S. Maryam Ghasemi, Jonas Krautter, Tara Gheshlaghi, Sergej Meschkov, Dennis R. E. Gnad, Mehdi B. Tahoori

Affiliation: Karlsruhe Institute of Technology (DE)

Complex systems are subject to various hardware and software defects and faults through the entire design and deployment lifecycle. Many of such defects originate at the electrical or circuit levels, but manifest as functional failures in the field. In this study, we present a methodology for embed- ding and employing software-controlled runtime variation and degradation sensors on a RISC-V SoC to enable system-level and functional testing in the field. We demonstrate the effectiveness of the entire platform through an FPGA implementation. Delay defects and path degradations are emulated by injecting artificial delay elements into the critical path of a specific instruction. We also emulate the effect of workload-induced runtime stress with tunable software-controlled power wasters. Combining various sensors, we show that transient fluctuations, which are caused by temperature or workload, can be effectively separated from persistent delay increase, which is caused by latent manufacturing defects or aging.

Maryam received her Bachelor's and Master's degrees from the University of Tehran in the field of Electrical Engineering-Digital Systems. In September 2022, she joined the CDNC group at the Karlsruhe Institute of Technology (KIT) as a PhD student under the supervision of Professor Mehdi Tahoori. Her areas of interest include Silicon Lifecycle Management (SLM), Silent Data Corruption (SDC), RISC-V processors, FPGAs, testing, and deep learning.

Best Paper Award Candidate

Cross-Layer Reliability Analysis of NVDLA Accelerators: Exploring the Configuration Space

Authors: Alessandro Veronesi 1 , Alessandro Nazzari 2 , Dario Passarello 2 , Milos Krstic 1, 3 , Michele Favalli 4 , Luca Cassano 2 , Antonio Miele 2 , Davide Bertozzi 5 , Cristiana Bolchini 1

Affiliations: 1 IHP - Microelectronics (DE), 2 Politecnico di Milano (IT), 3 University of Potsdam (DE), 4 University degli Studi di Ferrara (IT), 5 University of Manchester (UK)

Investigating the effects of Single Event Upset in domain-specific accelerators represents one of the key enablers to deploy Deep Neural Networks (DNNs) in mission-critical edge applications. Currently, reliability analyses related to DNNs mainly focus either on the DNNs model, at application level, or on the hardware accelerator, at architecture level. This paper presents a systematic cross-layer reliability analysis of NVIDIA Deep-Learning Accelerator, a popular family of industry-grade, open and free DNN accelerators. The goals are i) to analyze the propagation of faults from the hardware to the application level, and ii) to compare different architectural configurations. Our investigation delivers new insights into the performance-accuracy-reliability trade-off spanned by the configuration space of Deep Learning accelerators. In particular, the Failure in Time can be reduced up to 4.3x for the same DNN model accuracy and by up to 9.4x for the same performance, while accounting 6.5x inference latency and 1.1% accuracy drop, respectively.

Graduated in March 2020 at University of Ferrara (IT), A. Veronesi is at the moment PhD student at IHP - Microelectronics (DE).His research majorly focus on computer architecture, dependable AI systems, and cross-layer verification methodologies.

CGAN-based Automated Fault Injection

Authors: Troya Cagil Köylü, Cornelis Christiaan Berg, Praveen Vadnala

Affiliation: Riscure B.V. (NL)

Fault injection is a major threat to electronic devices. Consequently, developers or independent test labs spend significant time and effort in identifying fault injection vulnerabilities. While there are proposed methods to automate fault injection vulnerability identification, their performance depend on observing many successful glitches first to generate more of them. This takes a considerable amount of time and it is common for fault injection campaigns to produce no or very few successful glitches initially. To address this issue, we propose a conditional generative adversarial network (CGAN)-based automated fault injection method. Our method finds promising regions in the parameter space even without observing successful glitches, as well as adjusts itself after observing them. Experimental results show that our method proposes at least 1.3 times more successful glitch parameters than the state of the art in both voltage and electromagnetic (EM)-based fault injection.

Troya Koylu, born in 1992 in Turkey, completed his bachelors and masters studies in Bilkent University. In 2023, he was awarded the PhD title by the Delft University of Technology, with the thesis "Countermeasures against Fault Injection Attacks in Neural Networks and Processors". Since then, he is working in Riscure as a security analyst and researcher.

LAST-MODIFIED:20240325T152755Z SEQUENCE:1207179 LOCATION:Johan de Wittlaan 30\, 2517 JR Den Haag\, Zuid-Holland\, Netherlands GEO:52.08989950;4.28243397 X-LOCATION-DISPLAYNAME:Room A1 X-ACCESS:1 X-HITS:714 X-COLOR:66c2a5 X-SHOW-END-TIME:1 END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Amsterdam:20240523T110000 DTEND;TZID=Europe/Amsterdam:20240523T123000 UID:4CD5A05E-11B8-494E-A621-87CA617BE486 SUMMARY:​Regular Session 6 CREATED:20240313T095721Z DTSTAMP:20240313T095721Z URL:https://ets24.ewi.tudelft.nl/index.php/home/program/conference-program/regular-session-8 DESCRIPTION:\N \N \N Moderators:\N \N Ilia Polian\N \N 1\N \N , Alessandro Savino\N \N 2\N \N \N\N\N \N \N Affiliations:\N \N \N 1\N \N University of Stuttgart (DE),\N \N 2\N \N Politecnico di Torino (IT)\N \N\N\N \N \N Power Analysis Attack Against post-SAT Logic Locking schemes\N \N \N \N \N \N \N \N \N \N \N Authors:\N \N Nassim Riadi, Florent Bruguier, Pascal Benoit, Sophie Dupuis, Marie-Lise Flottes\N \N \N \N \N \N Affiliation:\N \N LIRMM,Univ. Montpellier/CNRS (FR)\N \N \N \N \N \N Abstract:\N \N \N \N \N Due to the globalization of the semiconductor industry, Integrated Circuits (ICs) and Intellectual Properties (IPs) are susceptible to specific threats. IP piracy, overproduction, and introduction of hardware Trojans can indeed compromise valuable design information and trust in the design flow. Logic Locking (LL) is one of the most popular Design-for-Trust techniques that aims to thwart these threats because of the wide range of risks it can prevent. This approach evolves from year to year in order to make it resistant to ever more advanced attacks. While most advanced LL solutions are assumed to be resistant against differential power analysis (DPA), we propose a new attack framework for challenging these approaches and show on several benchmarks that it is possible to reveal more than 88% of the key bits used for locking the designs thanks to DPA.\N \N \N \N \N \N Biography:\N \N \N \N \N Nassim riadi received his Master degree in integrated electronics systems from university of Montpellier In 2022 He is currently pursuing a PhD at Lirmm. His area of interest is design for trust with a particular interest in logic locking techniques.\N \N \N \N \N \N A Novel Power Analysis Attack against CRYSTALS-Dilithium Implementation\N \N \N \N \N \N \N \N \N \N \N Authors:\N \N Yong Liu\N \N 1\N \N , Yuejun Liu\N \N 1\N \N , Yongbin Zhou\N \N 1, 2\N \N , Yiwen Gao\N \N 1\N \N , Zehua Qiao\N \N 2\N \N , Huaxin Wang\N \N 1\N \N \N \N \N \N \N Affiliations:\N \N \N 1\N \N Nanjing University of Science and Technology (CN),\N \N 2\N \N Chinese Academy of Sciences (CN)\N \N \N \N \N \N Abstract:\N \N \N \N \N Post-Quantum Cryptography (PQC) was proposed due to the potential threats quantum computer attacks against conventional public key cryptosystems, and four PQC algorithms besides CRYSTALS-Dilithium (Dilithium for short) have so far been selected for National Institute of Standards and Technology (NIST) standardization. However, the selected algorithms are still vulnerable to side-channel attacks in practice, and their physical security need to be further evaluated. This paper proposes two efficient power analysis attacks against Dilithium implementation, the optimized fast two-stage approach and the single-bit approach, aiming at reducing the key guess space. Our findings reveal that the optimized approach outperforms the conservative approach and the fast two-stage approach proposed in ICCD 2021 by factors of 338 and 49, respectively. Similarly, compared to these two approaches, the single-bit approach achieves acceleration of 367 times and 53 times, respectively.\N \N \N \N \N \N Biography:\N \N \N \N \N Yong Liu is currently a master's student at Nanjing University of Science and Technology (CN).His main research interests include side-channel attacks and cryptographic engineering.\N \N \N \N \N \N Counteracting Rowhammer by Data Alternation\N \N \N \N \N \N \N \N \N \N \N Authors:\N \N Stefan A. Lung, Georgi Gaydadjiev, Said Hamdioui, Mottaqiallah Taouil\N \N \N \N \N \N Affiliation:\N \N Delft University of Technology (NL)\N \N \N \N \N \N Abstract:\N \N \N \N \N Modern DRAMs are vulnerable to Rowhammer attacks, demanding robust protection methods to mitigate these attacks. Existing solutions aim at increased resilience by improving design and/or adjusting operation parameters, limit row access count by throttling and prevent bit flips by timely row refreshing. However, scaling these methods for future DRAM technologies may incur significant costs in terms of area, power and/or latency. This study analyses the impact of the values of the neighbouring cells on victim cells and introduces a row alternation protection method, which is a novel approach that alternates the data of attacker rows on each access to lower the chance of bit flips in victim rows. Our analysis show that the minimum Rowhammer count to cause a bitflip in a particular cell does not only depend on vertical neighbours from the attacker row, but also on the value of the horizontal neighbours from the victim row as well as diagonal cells from the attacker row. Row alternation is able to protect the majority of the vulnerable cells (i.e., with 65%) for the DRAM used in our case study and in cases where unsuccessful it significantly increases the average minimum required Rowhammer account by 18%.\N \N \N \N \N \N Biography:\N \N \N \N \N Stefan Lung is a graduate from The Delft University of Technology. He received his bachelor's degree in Mechatronics from The Hague University of Applied Sciences and his master's degree Embedded Systems from The Delft University of Technology. He is currently employed at the Royal Netherlands Aerospace Centre as an embedded systems cybersecurity research and developer for aerospace and space applications. His interests are cybersecurity, hardware dependability, IC design and advanced computing architectures.\N \N \N \N \N\N X-ALT-DESC;FMTTYPE=text/html:

Moderators: Ilia Polian 1 , Alessandro Savino 2

Affiliations: 1 University of Stuttgart (DE), 2 Politecnico di Torino (IT)

Power Analysis Attack Against post-SAT Logic Locking schemes

Authors: Nassim Riadi, Florent Bruguier, Pascal Benoit, Sophie Dupuis, Marie-Lise Flottes

Affiliation: LIRMM,Univ. Montpellier/CNRS (FR)

Due to the globalization of the semiconductor industry, Integrated Circuits (ICs) and Intellectual Properties (IPs) are susceptible to specific threats. IP piracy, overproduction, and introduction of hardware Trojans can indeed compromise valuable design information and trust in the design flow. Logic Locking (LL) is one of the most popular Design-for-Trust techniques that aims to thwart these threats because of the wide range of risks it can prevent. This approach evolves from year to year in order to make it resistant to ever more advanced attacks. While most advanced LL solutions are assumed to be resistant against differential power analysis (DPA), we propose a new attack framework for challenging these approaches and show on several benchmarks that it is possible to reveal more than 88% of the key bits used for locking the designs thanks to DPA.

Nassim riadi received his Master degree in integrated electronics systems from university of Montpellier In 2022 He is currently pursuing a PhD at Lirmm. His area of interest is design for trust with a particular interest in logic locking techniques.

A Novel Power Analysis Attack against CRYSTALS-Dilithium Implementation

Authors: Yong Liu 1 , Yuejun Liu 1 , Yongbin Zhou 1, 2 , Yiwen Gao 1 , Zehua Qiao 2 , Huaxin Wang 1

Affiliations: 1 Nanjing University of Science and Technology (CN), 2 Chinese Academy of Sciences (CN)

Post-Quantum Cryptography (PQC) was proposed due to the potential threats quantum computer attacks against conventional public key cryptosystems, and four PQC algorithms besides CRYSTALS-Dilithium (Dilithium for short) have so far been selected for National Institute of Standards and Technology (NIST) standardization. However, the selected algorithms are still vulnerable to side-channel attacks in practice, and their physical security need to be further evaluated. This paper proposes two efficient power analysis attacks against Dilithium implementation, the optimized fast two-stage approach and the single-bit approach, aiming at reducing the key guess space. Our findings reveal that the optimized approach outperforms the conservative approach and the fast two-stage approach proposed in ICCD 2021 by factors of 338 and 49, respectively. Similarly, compared to these two approaches, the single-bit approach achieves acceleration of 367 times and 53 times, respectively.

Yong Liu is currently a master's student at Nanjing University of Science and Technology (CN).His main research interests include side-channel attacks and cryptographic engineering.

Counteracting Rowhammer by Data Alternation

Authors: Stefan A. Lung, Georgi Gaydadjiev, Said Hamdioui, Mottaqiallah Taouil

Affiliation: Delft University of Technology (NL)

Modern DRAMs are vulnerable to Rowhammer attacks, demanding robust protection methods to mitigate these attacks. Existing solutions aim at increased resilience by improving design and/or adjusting operation parameters, limit row access count by throttling and prevent bit flips by timely row refreshing. However, scaling these methods for future DRAM technologies may incur significant costs in terms of area, power and/or latency. This study analyses the impact of the values of the neighbouring cells on victim cells and introduces a row alternation protection method, which is a novel approach that alternates the data of attacker rows on each access to lower the chance of bit flips in victim rows. Our analysis show that the minimum Rowhammer count to cause a bitflip in a particular cell does not only depend on vertical neighbours from the attacker row, but also on the value of the horizontal neighbours from the victim row as well as diagonal cells from the attacker row. Row alternation is able to protect the majority of the vulnerable cells (i.e., with 65%) for the DRAM used in our case study and in cases where unsuccessful it significantly increases the average minimum required Rowhammer account by 18%.

Stefan Lung is a graduate from The Delft University of Technology. He received his bachelor's degree in Mechatronics from The Hague University of Applied Sciences and his master's degree Embedded Systems from The Delft University of Technology. He is currently employed at the Royal Netherlands Aerospace Centre as an embedded systems cybersecurity research and developer for aerospace and space applications. His interests are cybersecurity, hardware dependability, IC design and advanced computing architectures.

LAST-MODIFIED:20240507T145524Z SEQUENCE:4769883 LOCATION:Johan de Wittlaan 30\, 2517 JR Den Haag\, Zuid-Holland\, Netherlands GEO:52.08989950;4.28243397 X-LOCATION-DISPLAYNAME:Room Gaugain + Dali X-ACCESS:1 X-HITS:720 X-COLOR:66c2a5 X-SHOW-END-TIME:1 END:VEVENT BEGIN:VEVENT DTSTART;TZID=Europe/Amsterdam:20240523T140000 DTEND;TZID=Europe/Amsterdam:20240523T153000 UID:45AE86C5-890D-49FF-BB27-BD87C842D5CE SUMMARY:​Regular Session 7 CREATED:20240311T160816Z DTSTAMP:20240311T160816Z URL:https://ets24.ewi.tudelft.nl/index.php/home/program/conference-program/regular-session-7 DESCRIPTION:\N \N \N Moderator:\N \N Tara Ghasempouri\N \N\N\N \N \N Affiliation:\N \N Tallinn University of Technology (EE)\N \N\N\N \N \N Fault Sensitivity Analysis of Printed Bespoke Multilayer Perceptron Classifiers\N \N \N \N \N \N \N \N \N \N \N Authors:\N \N Priyanjana Pal\N \N 1\N \N , Florentia Afentaki\N \N 1, 2\N \N , Haibin Zhao\N \N 1\N \N , Gurol Saglam\N \N 1\N \N , Michael Hefenbrock\N \N 3\N \N , Georgios Zervakis\N \N 2\N \N , Michael Beigl\N \N 1\N \N , Mehdi B. Tahoori\N \N 1\N \N \N \N \N \N \N Affiliations:\N \N \N 1\N \N Karlsruhe Institute of Technology (DE),\N \N 2\N \N University of Patras (GR),\N \N 3\N \N RevoAI GmbH (DE)\N \N \N \N \N \N Abstract:\N \N \N \N \N Printed Electronics (PE) is an emerging technology with flexible substrates and ultra-low-cost manufacturing, providing an appealing alternative to traditional wafer-scale silicon fabrication. With the increasing integration of various printed neural network (NN) architectures in diverse applications, the reliability of printed circuits has become a critical concern. This work provides a comprehensive analysis of the fault sensitivity on a variety of classification tasks for various digital and analog realizations of printed multilayer perceptrons (MLPs). We further evaluate different digital architectures, i.e., generic, bespoke, and approximate, to provide a comprehensive fault analysis on different benchmark datasets.\N \N \N \N \N \N Biography:\N \N \N \N \N Priyanjana Pal received her B.Tech. in ECE from NIT Agartala in 2018 and M.Tech. in EE from IIT Gandhinagar in 2020. She worked as a Senior ESD engineer at Global Foundries, Bangalore for nearly three years. In 2022, she joined as a PhD researcher with Prof. Mehdi Tahoori's group at Karlsruhe Institute of Technology(KIT), Germany. Her current research interests are in circuit design with CAD tools, reliability testing of printed circuits, and designing ML-trained flexible neuromorphic circuits.\N \N \N \N \N \N Polynomial Formal Verification of Approximate Adders with Constant Cutwidth\N \N \N \N \N \N \N \N \N \N \N Authors:\N \N Mohamed Nadeem\N \N 1\N \N , Chandan Kumar Jha\N \N 1\N \N , Rolf Drechsler\N \N 2\N \N \N \N \N \N \N Affiliations:\N \N \N 1\N \N University of Bremen (DE),\N \N 2\N \N DFKI (DE)\N \N \N \N \N \N Abstract:\N \N \N \N \N In the context of digital circuits, formal verification methods have been well-studied to ensure their functional correctness. However, several verification methods fail to provide an upper bound for the time and space complexity. Therefore, Polynomial Formal Verification (PFV) has been introduced to address this problem. Unlike prior works, which have shown that approximate circuits can be verified in polynomial time, we show that approximate circuits with a constant cutwidth can be verified even in linear time. Since approximate circuits have become ubiquitous in error-resilient applications, it becomes essential to guarantee their correctness. While prior works have been limited to formal error analysis, we use Answer Set Programming (ASP) based formal verification to guarantee that the approximate circuit matches its functional specification. In this paper, we first show that several approximate adder circuits exhibit a constant cutwidth. We then provide a PFV approach that relies on this cutwidth as a structural property of the circuits to guarantee a linear-time verification w.r.t. the bitwidth using ASP. Finally, we evaluate several approximate adders in terms of the upper bound of the cutwidth, and verification time.\N \N \N \N \N \N Biography:\N \N \N \N \N Mohamed Nadeem is a PhD student in Computer Architecture group under the supervision of Prof. Rolf Drechsler at the University of Bremen. Prior to that, he completed my Master's degree in Computational logic at Techincal University of Dresden, where he was working in the Knowledge Representation and Human Reasoning Group. His Research interests are Knowledge Representation, Logic Synthesis, and Polynomial Formal Verification.\N \N \N \N\N X-ALT-DESC;FMTTYPE=text/html:

Moderator: Tara Ghasempouri

Affiliation: Tallinn University of Technology (EE)

Fault Sensitivity Analysis of Printed Bespoke Multilayer Perceptron Classifiers

Authors: Priyanjana Pal 1 , Florentia Afentaki 1, 2 , Haibin Zhao 1 , Gurol Saglam 1 , Michael Hefenbrock 3 , Georgios Zervakis 2 , Michael Beigl 1 , Mehdi B. Tahoori 1

Affiliations: 1 Karlsruhe Institute of Technology (DE), 2 University of Patras (GR), 3 RevoAI GmbH (DE)

Printed Electronics (PE) is an emerging technology with flexible substrates and ultra-low-cost manufacturing, providing an appealing alternative to traditional wafer-scale silicon fabrication. With the increasing integration of various printed neural network (NN) architectures in diverse applications, the reliability of printed circuits has become a critical concern. This work provides a comprehensive analysis of the fault sensitivity on a variety of classification tasks for various digital and analog realizations of printed multilayer perceptrons (MLPs). We further evaluate different digital architectures, i.e., generic, bespoke, and approximate, to provide a comprehensive fault analysis on different benchmark datasets.

Priyanjana Pal received her B.Tech. in ECE from NIT Agartala in 2018 and M.Tech. in EE from IIT Gandhinagar in 2020. She worked as a Senior ESD engineer at Global Foundries, Bangalore for nearly three years. In 2022, she joined as a PhD researcher with Prof. Mehdi Tahoori's group at Karlsruhe Institute of Technology(KIT), Germany. Her current research interests are in circuit design with CAD tools, reliability testing of printed circuits, and designing ML-trained flexible neuromorphic circuits.

Polynomial Formal Verification of Approximate Adders with Constant Cutwidth

Authors: Mohamed Nadeem 1 , Chandan Kumar Jha 1 , Rolf Drechsler 2

Affiliations: 1 University of Bremen (DE), 2 DFKI (DE)

In the context of digital circuits, formal verification methods have been well-studied to ensure their functional correctness. However, several verification methods fail to provide an upper bound for the time and space complexity. Therefore, Polynomial Formal Verification (PFV) has been introduced to address this problem. Unlike prior works, which have shown that approximate circuits can be verified in polynomial time, we show that approximate circuits with a constant cutwidth can be verified even in linear time. Since approximate circuits have become ubiquitous in error-resilient applications, it becomes essential to guarantee their correctness. While prior works have been limited to formal error analysis, we use Answer Set Programming (ASP) based formal verification to guarantee that the approximate circuit matches its functional specification. In this paper, we first show that several approximate adder circuits exhibit a constant cutwidth. We then provide a PFV approach that relies on this cutwidth as a structural property of the circuits to guarantee a linear-time verification w.r.t. the bitwidth using ASP. Finally, we evaluate several approximate adders in terms of the upper bound of the cutwidth, and verification time.

Mohamed Nadeem is a PhD student in Computer Architecture group under the supervision of Prof. Rolf Drechsler at the University of Bremen. Prior to that, he completed my Master's degree in Computational logic at Techincal University of Dresden, where he was working in the Knowledge Representation and Human Reasoning Group. His Research interests are Knowledge Representation, Logic Synthesis, and Polynomial Formal Verification.

LAST-MODIFIED:20240325T152818Z SEQUENCE:1207202 LOCATION:Johan de Wittlaan 30\, 2517 JR Den Haag\, Zuid-Holland\, Netherlands GEO:52.08989950;4.28243397 X-LOCATION-DISPLAYNAME:Room A1 X-ACCESS:1 X-HITS:648 X-COLOR:66c2a5 X-SHOW-END-TIME:1 END:VEVENT END:VCALENDAR