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SUMMARY:TSS@ETS Tutorial 1
CREATED:20240312T143754Z
DTSTAMP:20240312T143754Z
URL:https://ets24.ewi.tudelft.nl/index.php/home/program/conference-program/tss-and-ets-tutorial-1
DESCRIPTION:Silicon Fault Analysis (FA) equipment for security analysis\NPresenter: Jean-Pierre Seifert (TU Berlin)\NBiography\NJean-Pierre Seifert studied computer science and mathematics at Johann-Wolfgang-Goethe-University at Frankfurt/Main. He received the Ph.D. degree from Johann-Wolfgang-Goethe-University at Frankfurt/Main, in 2000, under the supervision of Prof. Dr. C. Schnorr, one of the most important theoretician in the field of secure information systems. He gained intensive practical experience working in the research and development departments for hardware security at Infineon, Munich, and Intel, USA. At Intel, from 2004 to 2006, he has been responsible for the design and integration of new CPU security instructions for microprocessors that are going to be integrated in all Intel microprocessors. From 2007 to 2008, he developed for Samsung Electronics the worldwide first commercial secure cell phone based on the Linux operating system. Since 2008, he has been a Professor heading the group Security in Telecommunications, Technical University of Berlin (TU Berlin). This professorship is at the same time related with the management of the identically named research field at Telekom Innovation Laboratories, the research and development institute of Deutsche Telekom at TU Berlin. He holds more than 40 patents in the field of computer security. In 2002, he has been honored by Infineon with the award Inventor of the Year and received two Intel Achievement Awards, in 2005, for his new CPU security instructions for the Intel microprocessors.
X-ALT-DESC;FMTTYPE=text/html:
Silicon Fault Analysis (FA) equipment for security analysis
Presenter: Jean-Pierre Seifert (TU Berlin)
Biography
Jean-Pierre Seifert studied computer science and mathematics at Johann-Wolfgang-Goethe-University at Frankfurt/Main. He received the Ph.D. degree from Johann-Wolfgang-Goethe-University at Frankfurt/Main, in 2000, under the supervision of Prof. Dr. C. Schnorr, one of the most important theoretician in the field of secure information systems. He gained intensive practical experience working in the research and development departments for hardware security at Infineon, Munich, and Intel, USA. At Intel, from 2004 to 2006, he has been responsible for the design and integration of new CPU security instructions for microprocessors that are going to be integrated in all Intel microprocessors. From 2007 to 2008, he developed for Samsung Electronics the worldwide first commercial secure cell phone based on the Linux operating system. Since 2008, he has been a Professor heading the group Security in Telecommunications, Technical University of Berlin (TU Berlin). This professorship is at the same time related with the management of the identically named research field at Telekom Innovation Laboratories, the research and development institute of Deutsche Telekom at TU Berlin. He holds more than 40 patents in the field of computer security. In 2002, he has been honored by Infineon with the award Inventor of the Year and received two Intel Achievement Awards, in 2005, for his new CPU security instructions for the Intel microprocessors.
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SUMMARY:TSS@ETS Tutorial 2
CREATED:20240312T143828Z
DTSTAMP:20240312T143828Z
URL:https://ets24.ewi.tudelft.nl/index.php/home/program/conference-program/tss-and-ets-tutorial-2
DESCRIPTION:Security of Generative AI and Generative AI for Security\NPresenters: Ramesh Karri (NYU, US) and Jeyavijayan (JV) Rajendran (Texas A&M University)\NThis tutorial comes with some hands-on training that is accessible here.\NBiography\NRamesh Karri is a Professor of Electrical and Computer Engineering at Tandon School of Engineering, New York University. He has a Ph.D. in Computer Science and Engineering, from the University of California at San Diego. His research and education activities span hardware cybersecurity including trustworthy ICs, processors and cyberphysical systems; security-aware computer aided design, test, verification, validation and reliability; nano meets security; metrics; benchmarks; hardware cybersecurity competitions; additive manufacturing security.\NHe has over 200 journal and conference publications including tutorials on Trustworthy Hardware in IEEE Computer (2) and Proceedings of the IEEE (5). His groups work on hardware cybersecurity was nominated for best paper awards (ICCD 2015 and DFTS 2015) and received awards at conferences (ITC 2014, CCS 2013, DFTS 2013 and VLSI Design 2012) and at competitions (ACM Student Research Competition at DAC 2012, ICCAD 2013, DAC 2014, ACM Grand Finals 2013, Kaspersky Challenge and Embedded Security Challenge).\NHe was the recipient of the Humboldt Fellowship and the National Science Foundation CAREER Award. He is the area director for cyber security of the NY State Center for Advanced Telecommunications Technologies at NYU-Poly; Co-founded the NYU Center for CyberSecurity -CCS ( cyber.nyu.edu ), co-founded the Trust-Hub ( trust-hub.org /) and founded and organizes the Embedded Security Challenge, the annual red team blue team event at NYU, ( www.nyu.edu/csaw2016/csaw-embedded ).\NHe co-founded the IEEE/ACM Symposium on Nanoscale Architectures (NANOARCH). He served as program/general chair of conferences including IEEE International Conference on Computer Design (ICCD), IEEE Symposium on Hardware Oriented Security and Trust (HOST), IEEE Symposium on Defect and Fault Tolerant Nano VLSI Systems (DFTS) NANOARCH, RFIDSEC 2015 and WISEC 2015. He serves on several program committees (DAC, ICCAD, HOST, ITC, VTS, ETS, ICCD, DTIS, WIFS).\NHe was the Associate Editor of IEEE Transactions on Information Forensics and Security (2010-2014), IEEE Transactions on CAD (2014-present), ACM Journal of Emerging Computing Technologies (2007-present), ACM Transactions on Design Automation of Electronic Systems (2014-present), IEEE Access (2015-present), IEEE Transactions on Emerging Technologies in Computing (2015-present), IEEE Design and Test (2015-present) and IEEE Embedded Systems Letters (2016-present). He served as an IEEE Computer Society Distinguished Visitor (2013-2015). He is on the Executive Committee of IEEE/ACM Design Automation Conference initiating and leading the Security@DAC initiative (2014-2017). He has delivered invited keynotes, talks, and tutorials on Hardware Security and Trust (ESRF, DAC, DATE, VTS, ITC, ICCD, NATW, LATW, CROSSING etc).
X-ALT-DESC;FMTTYPE=text/html:
Security of Generative AI and Generative AI for Security
This tutorial comes with some hands-on training that is accessible here.
Biography
Ramesh Karri is a Professor of Electrical and Computer Engineering at Tandon School of Engineering, New York University. He has a Ph.D. in Computer Science and Engineering, from the University of California at San Diego. His research and education activities span hardware cybersecurity including trustworthy ICs, processors and cyberphysical systems; security-aware computer aided design, test, verification, validation and reliability; nano meets security; metrics; benchmarks; hardware cybersecurity competitions; additive manufacturing security.
He has over 200 journal and conference publications including tutorials on Trustworthy Hardware in IEEE Computer (2) and Proceedings of the IEEE (5). His groups work on hardware cybersecurity was nominated for best paper awards (ICCD 2015 and DFTS 2015) and received awards at conferences (ITC 2014, CCS 2013, DFTS 2013 and VLSI Design 2012) and at competitions (ACM Student Research Competition at DAC 2012, ICCAD 2013, DAC 2014, ACM Grand Finals 2013, Kaspersky Challenge and Embedded Security Challenge).
He was the recipient of the Humboldt Fellowship and the National Science Foundation CAREER Award. He is the area director for cyber security of the NY State Center for Advanced Telecommunications Technologies at NYU-Poly; Co-founded the NYU Center for CyberSecurity -CCS ( cyber.nyu.edu ), co-founded the Trust-Hub ( trust-hub.org /) and founded and organizes the Embedded Security Challenge, the annual red team blue team event at NYU, ( www.nyu.edu/csaw2016/csaw-embedded ).
He co-founded the IEEE/ACM Symposium on Nanoscale Architectures (NANOARCH). He served as program/general chair of conferences including IEEE International Conference on Computer Design (ICCD), IEEE Symposium on Hardware Oriented Security and Trust (HOST), IEEE Symposium on Defect and Fault Tolerant Nano VLSI Systems (DFTS) NANOARCH, RFIDSEC 2015 and WISEC 2015. He serves on several program committees (DAC, ICCAD, HOST, ITC, VTS, ETS, ICCD, DTIS, WIFS).
He was the Associate Editor of IEEE Transactions on Information Forensics and Security (2010-2014), IEEE Transactions on CAD (2014-present), ACM Journal of Emerging Computing Technologies (2007-present), ACM Transactions on Design Automation of Electronic Systems (2014-present), IEEE Access (2015-present), IEEE Transactions on Emerging Technologies in Computing (2015-present), IEEE Design and Test (2015-present) and IEEE Embedded Systems Letters (2016-present). He served as an IEEE Computer Society Distinguished Visitor (2013-2015). He is on the Executive Committee of IEEE/ACM Design Automation Conference initiating and leading the Security@DAC initiative (2014-2017). He has delivered invited keynotes, talks, and tutorials on Hardware Security and Trust (ESRF, DAC, DATE, VTS, ITC, ICCD, NATW, LATW, CROSSING etc).
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SUMMARY:TSS@ETS Tutorial 1
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DTSTAMP:20240312T143926Z
URL:https://ets24.ewi.tudelft.nl/index.php/home/program/conference-program/tss-and-ets-tutorial-3
DESCRIPTION:Silicon Fault Analysis (FA) equipment for security analysis\NPresenter: Jean-Pierre Seifert (TU Berlin)\NBiography\NJean-Pierre Seifert studied computer science and mathematics at Johann-Wolfgang-Goethe-University at Frankfurt/Main. He received the Ph.D. degree from Johann-Wolfgang-Goethe-University at Frankfurt/Main, in 2000, under the supervision of Prof. Dr. C. Schnorr, one of the most important theoretician in the field of secure information systems. He gained intensive practical experience working in the research and development departments for hardware security at Infineon, Munich, and Intel, USA. At Intel, from 2004 to 2006, he has been responsible for the design and integration of new CPU security instructions for microprocessors that are going to be integrated in all Intel microprocessors. From 2007 to 2008, he developed for Samsung Electronics the worldwide first commercial secure cell phone based on the Linux operating system. Since 2008, he has been a Professor heading the group Security in Telecommunications, Technical University of Berlin (TU Berlin). This professorship is at the same time related with the management of the identically named research field at Telekom Innovation Laboratories, the research and development institute of Deutsche Telekom at TU Berlin. He holds more than 40 patents in the field of computer security. In 2002, he has been honored by Infineon with the award Inventor of the Year and received two Intel Achievement Awards, in 2005, for his new CPU security instructions for the Intel microprocessors.
X-ALT-DESC;FMTTYPE=text/html:
Silicon Fault Analysis (FA) equipment for security analysis
Presenter: Jean-Pierre Seifert (TU Berlin)
Biography
Jean-Pierre Seifert studied computer science and mathematics at Johann-Wolfgang-Goethe-University at Frankfurt/Main. He received the Ph.D. degree from Johann-Wolfgang-Goethe-University at Frankfurt/Main, in 2000, under the supervision of Prof. Dr. C. Schnorr, one of the most important theoretician in the field of secure information systems. He gained intensive practical experience working in the research and development departments for hardware security at Infineon, Munich, and Intel, USA. At Intel, from 2004 to 2006, he has been responsible for the design and integration of new CPU security instructions for microprocessors that are going to be integrated in all Intel microprocessors. From 2007 to 2008, he developed for Samsung Electronics the worldwide first commercial secure cell phone based on the Linux operating system. Since 2008, he has been a Professor heading the group Security in Telecommunications, Technical University of Berlin (TU Berlin). This professorship is at the same time related with the management of the identically named research field at Telekom Innovation Laboratories, the research and development institute of Deutsche Telekom at TU Berlin. He holds more than 40 patents in the field of computer security. In 2002, he has been honored by Infineon with the award Inventor of the Year and received two Intel Achievement Awards, in 2005, for his new CPU security instructions for the Intel microprocessors.
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SUMMARY:TSS@ETS Tutorial 2
CREATED:20240312T144437Z
DTSTAMP:20240312T144437Z
URL:https://ets24.ewi.tudelft.nl/index.php/home/program/conference-program/tss-and-ets-tutorial-5
DESCRIPTION:Security of Generative AI and Generative AI for Security\NPresenters: Ramesh Karri (NYU, US) and Jeyavijayan (JV) Rajendran (Texas A&M University)\NThis tutorial comes with some hands-on training that is accessible here.\NBiography\NRamesh Karri is a Professor of Electrical and Computer Engineering at Tandon School of Engineering, New York University. He has a Ph.D. in Computer Science and Engineering, from the University of California at San Diego. His research and education activities span hardware cybersecurity including trustworthy ICs, processors and cyberphysical systems; security-aware computer aided design, test, verification, validation and reliability; nano meets security; metrics; benchmarks; hardware cybersecurity competitions; additive manufacturing security.\NHe has over 200 journal and conference publications including tutorials on Trustworthy Hardware in IEEE Computer (2) and Proceedings of the IEEE (5). His groups work on hardware cybersecurity was nominated for best paper awards (ICCD 2015 and DFTS 2015) and received awards at conferences (ITC 2014, CCS 2013, DFTS 2013 and VLSI Design 2012) and at competitions (ACM Student Research Competition at DAC 2012, ICCAD 2013, DAC 2014, ACM Grand Finals 2013, Kaspersky Challenge and Embedded Security Challenge).\NHe was the recipient of the Humboldt Fellowship and the National Science Foundation CAREER Award. He is the area director for cyber security of the NY State Center for Advanced Telecommunications Technologies at NYU-Poly; Co-founded the NYU Center for CyberSecurity -CCS ( cyber.nyu.edu ), co-founded the Trust-Hub ( trust-hub.org /) and founded and organizes the Embedded Security Challenge, the annual red team blue team event at NYU, ( www.nyu.edu/csaw2016/csaw-embedded ).\NHe co-founded the IEEE/ACM Symposium on Nanoscale Architectures (NANOARCH). He served as program/general chair of conferences including IEEE International Conference on Computer Design (ICCD), IEEE Symposium on Hardware Oriented Security and Trust (HOST), IEEE Symposium on Defect and Fault Tolerant Nano VLSI Systems (DFTS) NANOARCH, RFIDSEC 2015 and WISEC 2015. He serves on several program committees (DAC, ICCAD, HOST, ITC, VTS, ETS, ICCD, DTIS, WIFS).\NHe was the Associate Editor of IEEE Transactions on Information Forensics and Security (2010-2014), IEEE Transactions on CAD (2014-present), ACM Journal of Emerging Computing Technologies (2007-present), ACM Transactions on Design Automation of Electronic Systems (2014-present), IEEE Access (2015-present), IEEE Transactions on Emerging Technologies in Computing (2015-present), IEEE Design and Test (2015-present) and IEEE Embedded Systems Letters (2016-present). He served as an IEEE Computer Society Distinguished Visitor (2013-2015). He is on the Executive Committee of IEEE/ACM Design Automation Conference initiating and leading the Security@DAC initiative (2014-2017). He has delivered invited keynotes, talks, and tutorials on Hardware Security and Trust (ESRF, DAC, DATE, VTS, ITC, ICCD, NATW, LATW, CROSSING etc).
X-ALT-DESC;FMTTYPE=text/html:
Security of Generative AI and Generative AI for Security
This tutorial comes with some hands-on training that is accessible here.
Biography
Ramesh Karri is a Professor of Electrical and Computer Engineering at Tandon School of Engineering, New York University. He has a Ph.D. in Computer Science and Engineering, from the University of California at San Diego. His research and education activities span hardware cybersecurity including trustworthy ICs, processors and cyberphysical systems; security-aware computer aided design, test, verification, validation and reliability; nano meets security; metrics; benchmarks; hardware cybersecurity competitions; additive manufacturing security.
He has over 200 journal and conference publications including tutorials on Trustworthy Hardware in IEEE Computer (2) and Proceedings of the IEEE (5). His groups work on hardware cybersecurity was nominated for best paper awards (ICCD 2015 and DFTS 2015) and received awards at conferences (ITC 2014, CCS 2013, DFTS 2013 and VLSI Design 2012) and at competitions (ACM Student Research Competition at DAC 2012, ICCAD 2013, DAC 2014, ACM Grand Finals 2013, Kaspersky Challenge and Embedded Security Challenge).
He was the recipient of the Humboldt Fellowship and the National Science Foundation CAREER Award. He is the area director for cyber security of the NY State Center for Advanced Telecommunications Technologies at NYU-Poly; Co-founded the NYU Center for CyberSecurity -CCS ( cyber.nyu.edu ), co-founded the Trust-Hub ( trust-hub.org /) and founded and organizes the Embedded Security Challenge, the annual red team blue team event at NYU, ( www.nyu.edu/csaw2016/csaw-embedded ).
He co-founded the IEEE/ACM Symposium on Nanoscale Architectures (NANOARCH). He served as program/general chair of conferences including IEEE International Conference on Computer Design (ICCD), IEEE Symposium on Hardware Oriented Security and Trust (HOST), IEEE Symposium on Defect and Fault Tolerant Nano VLSI Systems (DFTS) NANOARCH, RFIDSEC 2015 and WISEC 2015. He serves on several program committees (DAC, ICCAD, HOST, ITC, VTS, ETS, ICCD, DTIS, WIFS).
He was the Associate Editor of IEEE Transactions on Information Forensics and Security (2010-2014), IEEE Transactions on CAD (2014-present), ACM Journal of Emerging Computing Technologies (2007-present), ACM Transactions on Design Automation of Electronic Systems (2014-present), IEEE Access (2015-present), IEEE Transactions on Emerging Technologies in Computing (2015-present), IEEE Design and Test (2015-present) and IEEE Embedded Systems Letters (2016-present). He served as an IEEE Computer Society Distinguished Visitor (2013-2015). He is on the Executive Committee of IEEE/ACM Design Automation Conference initiating and leading the Security@DAC initiative (2014-2017). He has delivered invited keynotes, talks, and tutorials on Hardware Security and Trust (ESRF, DAC, DATE, VTS, ITC, ICCD, NATW, LATW, CROSSING etc).
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SUMMARY:Embedded Tutorial 1
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URL:https://ets24.ewi.tudelft.nl/index.php/home/program/conference-program/embedded-totorial-1
DESCRIPTION:\N \N \N Moderator:\N \N Maksim Jenihhin\N \N\N\N \N \N Affiliation:\N \N Tallinn University of Technology (EE)\N \N\N\N \N \N Silent Data Corruptions in Computing Systems: Early Predictions and Large-Scale Measurements\N \N \N \N \N \N \N \N \N \N \N Authors:\N \N Dimitris Gizopoulos\N \N 1\N \N , Harish Dixit\N \N 2\N \N \N \N \N \N \N Affiliations:\N \N \N 1\N \N University of Athens (GR),\N \N 2\N \N Meta Inc (US)\N \N \N \N \N \N Abstract:\N \N \N \N \N Silent Data Corruptions (SDCs) due to CPU defects is a critical threat to the quality of large-scale computing in different application domains: cloud computing, high- performance computing, and edge computing. We focus on recent efforts to correlate early simulation-based predictions about the likelihood, rates, severity, and root causes of SDCs on one hand and large-scale in-field studied in the cloud on the other. The analysis of the findings of this pre-silicon and post-deployment correlation can drive effective protection decisions either at the hardware or at the software levels.\N \N \N \N \N \N Biography:\N \N \N \N \N \N \N Coordinating Presenter: Dimitris Gizopoulos\N \N is Professor at the Department of Informatics & Telecommunications of the University of Athens leading the Computer Architecture Lab. The group's research focuses on the dependability, energy-efficiency, and performance of computer architectures. Gizopoulos has published more than 190 papers in conferences and journals, has served and is currently serving as Associate Editor for several IEEE and ACM Transactions and Magazines and as member of Program, Organizing and Steering Committees of IEEE and ACM conferences. Gizopoulos is an IEEE Fellow, a Golden Core member of the IEEE Computer Society and a Distinguished ACM member.\N \N \N \N Co-Presenter 1: Harish Dixit\N \N is a Principal Engineer (Release to Production) at Meta. Harish and team work on reliability, analytics and performance evaluation for all of deployed fleet of servers. Harish leads the efforts to deal with silent data corruptions within Meta infrastructure across CPUs, GPUs and ASICs, and has been working across different layers of the stack to mitigate the effects of silent data corruption on production applications. Harish has over 20 patent filings across system architecture and communication domains.\N \N \N \N\N
X-ALT-DESC;FMTTYPE=text/html:
Moderator: Maksim Jenihhin
Affiliation: Tallinn University of Technology (EE)
Silent Data Corruptions in Computing Systems: Early Predictions and Large-Scale Measurements
Authors: Dimitris Gizopoulos 1 , Harish Dixit 2
Affiliations: 1 University of Athens (GR), 2 Meta Inc (US)
Silent Data Corruptions (SDCs) due to CPU defects is a critical threat to the quality of large-scale computing in different application domains: cloud computing, high- performance computing, and edge computing. We focus on recent efforts to correlate early simulation-based predictions about the likelihood, rates, severity, and root causes of SDCs on one hand and large-scale in-field studied in the cloud on the other. The analysis of the findings of this pre-silicon and post-deployment correlation can drive effective protection decisions either at the hardware or at the software levels.
Coordinating Presenter: Dimitris Gizopoulos is Professor at the Department of Informatics & Telecommunications of the University of Athens leading the Computer Architecture Lab. The group's research focuses on the dependability, energy-efficiency, and performance of computer architectures. Gizopoulos has published more than 190 papers in conferences and journals, has served and is currently serving as Associate Editor for several IEEE and ACM Transactions and Magazines and as member of Program, Organizing and Steering Committees of IEEE and ACM conferences. Gizopoulos is an IEEE Fellow, a Golden Core member of the IEEE Computer Society and a Distinguished ACM member.
Co-Presenter 1: Harish Dixit is a Principal Engineer (Release to Production) at Meta. Harish and team work on reliability, analytics and performance evaluation for all of deployed fleet of servers. Harish leads the efforts to deal with silent data corruptions within Meta infrastructure across CPUs, GPUs and ASICs, and has been working across different layers of the stack to mitigate the effects of silent data corruption on production applications. Harish has over 20 patent filings across system architecture and communication domains.
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SUMMARY:Embedded Tutorial 2
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URL:https://ets24.ewi.tudelft.nl/index.php/home/program/conference-program/embedded-totorial-2
DESCRIPTION:\N \N \N Moderator:\N \N Paolo Bernardi\N \N\N\N \N \N Affiliation:\N \N Politecnico di Torino (IT)\N \N\N\N \N \N Lifecycle Management of Emerging Memories\N \N \N \N \N \N \N \N \N \N \N Authors:\N \N Moritz Fieback\N \N 1\N \N , Leticia Maria Bolzani Poehls\N \N 2\N \N \N \N \N \N \N Affiliations:\N \N \N 1\N \N Delft University of Technology (NL),\N \N 2\N \N RWTH Aachen University (DE)\N \N \N \N \N \N Abstract:\N \N \N \N \N Traditional charge-based memories such as dynamic RAM (DRAM) and flash are facing more and more manufacturing, reliability, energy, and speed issues. A growing group of emerging memory technologies, such resistive RAM (RRAM), spin-transfer torque magnetic RAM (STT-MRAM), phase change memory (PCM), and Ferroelectric (Fe) devices (e.g., FeFET, FeRAM), address these problems. Nonetheless, these technologies are also not perfect, and thus special care must be taken to ensure that the lifecycle management, from design to obsolescence, of these memories is as optimal as possible. Lifecycle management is being developed for traditional technologies, but these are not optimized for emerging memories yet. In this paper, we present the first steps of lifecycle management for emerging memories. We analyze the different lifecycle phases that exist for two case studies on RRAM and FeFET-based memories. In this analysis, we identify how the phases affect each other and which optimizations are possible by analyzing the complete lifecycle. Finally, we compare the lifecycle phases of these two emerging memories to see how a unified approach can be developed.\N \N \N \N \N \N Biography:\N \N \N \N \N \N \N Coordinating Presenter: Leticia Maria Bolzani Poehls\N \N received her PhD degree in Computer Engineering from Politecnico di Torino (Italy) in 2008. From 2010 to 2022 she was professor at Pontifical Catholic University of Rio Grande do Sul (PUCRS) in Brazil. Currently, she leads the research group of “Test & Reliability of Emerging Memories” at at the Chair of Integrated Digital Systems, RWTH Aachen University (Germany). She is member of the Steering Committee for the IEEE LATS and BELAS. Finally, she received the 2021 JETTA-TTTC Best Paper Award and the IEEE Latin American Test Symposium (LATS2022) Best Paper Award.\N \N \N \N 1: Moritz Fieback\N \N received his PhD degree from Delft University of Technology in the Netherlands in 2022. Currently, he is working as an assistant professor in the same university. His research interests include device and defect modeling, test and reliability of emerging memories, and computation-in-memory systems. He has co-authored over 40 articles and won 3 best paper awards.\N \N \N \N\N
X-ALT-DESC;FMTTYPE=text/html:
Moderator: Paolo Bernardi
Affiliation: Politecnico di Torino (IT)
Lifecycle Management of Emerging Memories
Authors: Moritz Fieback 1 , Leticia Maria Bolzani Poehls 2
Affiliations: 1 Delft University of Technology (NL), 2 RWTH Aachen University (DE)
Traditional charge-based memories such as dynamic RAM (DRAM) and flash are facing more and more manufacturing, reliability, energy, and speed issues. A growing group of emerging memory technologies, such resistive RAM (RRAM), spin-transfer torque magnetic RAM (STT-MRAM), phase change memory (PCM), and Ferroelectric (Fe) devices (e.g., FeFET, FeRAM), address these problems. Nonetheless, these technologies are also not perfect, and thus special care must be taken to ensure that the lifecycle management, from design to obsolescence, of these memories is as optimal as possible. Lifecycle management is being developed for traditional technologies, but these are not optimized for emerging memories yet. In this paper, we present the first steps of lifecycle management for emerging memories. We analyze the different lifecycle phases that exist for two case studies on RRAM and FeFET-based memories. In this analysis, we identify how the phases affect each other and which optimizations are possible by analyzing the complete lifecycle. Finally, we compare the lifecycle phases of these two emerging memories to see how a unified approach can be developed.
Coordinating Presenter: Leticia Maria Bolzani Poehls received her PhD degree in Computer Engineering from Politecnico di Torino (Italy) in 2008. From 2010 to 2022 she was professor at Pontifical Catholic University of Rio Grande do Sul (PUCRS) in Brazil. Currently, she leads the research group of “Test & Reliability of Emerging Memories” at at the Chair of Integrated Digital Systems, RWTH Aachen University (Germany). She is member of the Steering Committee for the IEEE LATS and BELAS. Finally, she received the 2021 JETTA-TTTC Best Paper Award and the IEEE Latin American Test Symposium (LATS2022) Best Paper Award.
1: Moritz Fieback received his PhD degree from Delft University of Technology in the Netherlands in 2022. Currently, he is working as an assistant professor in the same university. His research interests include device and defect modeling, test and reliability of emerging memories, and computation-in-memory systems. He has co-authored over 40 articles and won 3 best paper awards.
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DESCRIPTION:\N \N \N Moderator:\N \N Leticia Bolzani-Poehls\N \N\N\N \N \N Affiliation:\N \N RTWH Aachen University (DE)\N \N\N\N \N \N Approximate Fault-Tolerant Neural Network Systems\N \N \N \N \N \N \N \N \N \N \N Authors:\N \N Marcello Traiola\N \N 1\N \N , Salvatore Pappalardo\N \N 2\N \N , Ali Piri\N \N 2\N \N , Annachiara Ruospo\N \N 3\N \N , Bastien Deveautour\N \N 2\N \N , Ernesto Sanchez\N \N 3\N \N , Alberto Bosio\N \N 2\N \N , Sepide Saeedi\N \N 3\N \N , Alessio Carpegna\N \N 3\N \N , Anil Bayram Gogebakan\N \N 3\N \N , Enrico Magliano\N \N 3\N \N , Alessandro Savino\N \N 3\N \N \N \N \N \N \N Affiliations:\N \N \N 1\N \N University Rennes, CNRS (FR),\N \N 2\N \N Univ Lyon, ECL, INSA (FR),\N \N 3\N \N Politecnico di Torino (IT)\N \N \N \N \N \N Abstract:\N \N \N \N \N This paper aims to comprehensively explore challenges and opportunities to design highly efficient Neural Network (NN) systems through Approximate Computing (AxC) techniques while ensuring fault tolerance properties. By highlighting the intrinsic conflicting goals of AxC and fault tolerance principles, the study aims to stimulate and contribute to a deeper understanding of how important it is to consider fault tolerance requirements while designing approximate-computingbased systems. This is key to developing highly efficient faulttolerant architectures for Neural Networks.\N \N \N \N \N \N Biography:\N \N \N \N \N \N \N Coordinating Presenter: Marcello Traiola\N \N received the Laurea degree (MSc) in Computer Engineering in 2016 from the University of Naples Federico II, Italy, and the Ph.D. degree in Computer Engineering in 2019 from the University of Montpellier, France. Currently, he is a faculty research scientist with the Inria Research Institute at the IRISA laboratory in Rennes, France, in the TARAN research team. Previously, he was a postdoctoral researcher at Inria Rennes for one year and earlier at the Lyon Institute of Nanotechnology, Ecole Centrale de Lyon, in France, for almost two years. His main research topics are emerging computing paradigms (approximate computing, in-memory computing) with a special interest in hardware design, testing, and reliability. He is co-author of 3 book chapters, 10 articles in international journals, and more than 60 articles in international conferences and workshops. He served as a committee member and organizing member of several international conferences. Among others, he serves as Review and Programme Operations Chair of DATE (2023-2025), and as General Chair of IOLTS 2024. He actively participates in several national projects (also as work package leader for Inria) and co-supervises Master’s and PhD students and Postdocs. He is an IEEE member and responsible for the Test Technical Technology Community (TTTC) website. More information at\N \N https://people.rennes.inria.fr/Marcello.Traiola\N \N .\N \N \N \N Co-Presenter 1: Alessandro Savino\N \N is an Associate Professor in the Department of Control and Computer Engineering at Politecnico di Torino (Italy). He holds a Ph.D. (2009) and an M.S. equivalent (2005) in Computer Engineering and Information Technology from the Politecnico di Torino in Italy. His research contributions include approximate computing, reliability analysis, safety-critical systems, software-based Self-tests, and image analysis. He has been part of the program and organizing committee of several IEEE and INSTICC conferences and has served as a reviewer of IEEE conferences and journals. His research interests include operating systems, imaging algorithms, machine learning, evolutionary algorithms, graphic user interface experience, and audio manipulation. He is IEEE Senior Member and EBS chair of TTTC.\N \N \N \N Co-Presenter 2: Alberto Bosio\N \N has carried out all his studies in Italy, including the Ph.D. in Computer Engineering in the area of digital systems dependability at the Politecnico di Torino (Italy) in 2006. He joined the University of Montpellier in 2007 as Associate Professor and from 2018 he is a Full Professor at the Ecole Centrale de Lyon - Institute of Nanotechnology. His research activity focuses on the dependability of computing systems, design and test of emerging computing architectures and the approximate computing paradigm. The works carried out over 14 years of career let him be the co-author of 4 books, 4 book-chapters, 4 patents, 54 papers in international journals and 164 papers in international conferences and workshops. He received several best paper awards in international conferences including IEEE DFT 2020, IEEE DDECS 2016 and IEEE VTS 2016. He had supervised 16 Ph.D. students. He actively participated and coordinated up to 15 european- and national-funded projects and research contracts with industrial partners. He served as committee and organizing member in several international conferences, He was the program chair of DDECS 2019, DDECS 2020 and he is the Vice-Program chair of ETS 2022 (and program chair of ETS 2023). He co-organized the last four editions of the international workshop on Approximate Computing co-located at ETS’18, DATE’19, DAC’20 and ICCAD’21. He served as steering committee member in DDECS. He was guest editor for IEEE D&T, ACM JETC, ELSEVIER Microelectronics & Reliability, ELSEVIER Future Generation Computer Systems and World Scientific Journal of Circuits, Systems and Computers. He is a member of the IEEE and the Co-Chair of the European Test Technical Technology Council (eTTTC). For more information, please see\N \N http://perso.ec-lyon.fr/alberto.bosio/\N \N .\N \N \N \N\N
X-ALT-DESC;FMTTYPE=text/html:
Affiliations: 1 University Rennes, CNRS (FR), 2 Univ Lyon, ECL, INSA (FR), 3 Politecnico di Torino (IT)
This paper aims to comprehensively explore challenges and opportunities to design highly efficient Neural Network (NN) systems through Approximate Computing (AxC) techniques while ensuring fault tolerance properties. By highlighting the intrinsic conflicting goals of AxC and fault tolerance principles, the study aims to stimulate and contribute to a deeper understanding of how important it is to consider fault tolerance requirements while designing approximate-computingbased systems. This is key to developing highly efficient faulttolerant architectures for Neural Networks.
Coordinating Presenter: Marcello Traiola received the Laurea degree (MSc) in Computer Engineering in 2016 from the University of Naples Federico II, Italy, and the Ph.D. degree in Computer Engineering in 2019 from the University of Montpellier, France. Currently, he is a faculty research scientist with the Inria Research Institute at the IRISA laboratory in Rennes, France, in the TARAN research team. Previously, he was a postdoctoral researcher at Inria Rennes for one year and earlier at the Lyon Institute of Nanotechnology, Ecole Centrale de Lyon, in France, for almost two years. His main research topics are emerging computing paradigms (approximate computing, in-memory computing) with a special interest in hardware design, testing, and reliability. He is co-author of 3 book chapters, 10 articles in international journals, and more than 60 articles in international conferences and workshops. He served as a committee member and organizing member of several international conferences. Among others, he serves as Review and Programme Operations Chair of DATE (2023-2025), and as General Chair of IOLTS 2024. He actively participates in several national projects (also as work package leader for Inria) and co-supervises Master’s and PhD students and Postdocs. He is an IEEE member and responsible for the Test Technical Technology Community (TTTC) website. More information at https://people.rennes.inria.fr/Marcello.Traiola .
Co-Presenter 1: Alessandro Savino is an Associate Professor in the Department of Control and Computer Engineering at Politecnico di Torino (Italy). He holds a Ph.D. (2009) and an M.S. equivalent (2005) in Computer Engineering and Information Technology from the Politecnico di Torino in Italy. His research contributions include approximate computing, reliability analysis, safety-critical systems, software-based Self-tests, and image analysis. He has been part of the program and organizing committee of several IEEE and INSTICC conferences and has served as a reviewer of IEEE conferences and journals. His research interests include operating systems, imaging algorithms, machine learning, evolutionary algorithms, graphic user interface experience, and audio manipulation. He is IEEE Senior Member and EBS chair of TTTC.
Co-Presenter 2: Alberto Bosio has carried out all his studies in Italy, including the Ph.D. in Computer Engineering in the area of digital systems dependability at the Politecnico di Torino (Italy) in 2006. He joined the University of Montpellier in 2007 as Associate Professor and from 2018 he is a Full Professor at the Ecole Centrale de Lyon - Institute of Nanotechnology. His research activity focuses on the dependability of computing systems, design and test of emerging computing architectures and the approximate computing paradigm. The works carried out over 14 years of career let him be the co-author of 4 books, 4 book-chapters, 4 patents, 54 papers in international journals and 164 papers in international conferences and workshops. He received several best paper awards in international conferences including IEEE DFT 2020, IEEE DDECS 2016 and IEEE VTS 2016. He had supervised 16 Ph.D. students. He actively participated and coordinated up to 15 european- and national-funded projects and research contracts with industrial partners. He served as committee and organizing member in several international conferences, He was the program chair of DDECS 2019, DDECS 2020 and he is the Vice-Program chair of ETS 2022 (and program chair of ETS 2023). He co-organized the last four editions of the international workshop on Approximate Computing co-located at ETS’18, DATE’19, DAC’20 and ICCAD’21. He served as steering committee member in DDECS. He was guest editor for IEEE D&T, ACM JETC, ELSEVIER Microelectronics & Reliability, ELSEVIER Future Generation Computer Systems and World Scientific Journal of Circuits, Systems and Computers. He is a member of the IEEE and the Co-Chair of the European Test Technical Technology Council (eTTTC). For more information, please see http://perso.ec-lyon.fr/alberto.bosio/ .
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DESCRIPTION:\N \N \N Moderator:\N \N Stefano di Carlo\N \N\N\N \N \N Affiliation:\N \N Politecnico di Torino (IT)\N \N\N\N \N \N Silent Data Corruption from Timing Marginalities Due to Process Variations\N \N \N \N \N \N \N \N \N \N \N Author:\N \N Adit D. Singh\N \N \N \N \N \N Affiliation:\N \N Auburn University (US)\N \N \N \N \N \N Abstract:\N \N \N \N \N We make the case, supported by recently published industrial data, that many of the hard to detect failures that escape post manufacturing tests and contribute to silent data corruption are timing failures resulting from significant increases in the delay of random circuit paths caused by manufacturing process variations. However, these are challenging to target at test because high coverage scan path delay tests are impractical. This research is investigating the characteristics of extreme statistical outlier slow paths in circuits with the goal of finding alternate test methods to detect and screen them out. We are particularly focused on low voltage operation because circuit delays due to process variations are greatly accentuated in that environment. A significant observation from this study is that delay increases from variability are not uniformly distributed among the gates in a potentially failing slow path. Instead, most of the delay increase is concentrated in a single gate. This suggests that node oriented TDF timing tests may also detect many of the timing failures caused by process variations. We show how the test voltage and clock timing of the applied TDF scan tests can be optimized to enhance the likelihood of detection of these marginal timing parts.\N \N \N \N \N \N Biography:\N \N \N \N \N Adit Singh is Godbold Endowed Chair and Professor of Electrical and Computer Engineering at Auburn University, USA. He earlier served on the faculties of the University of Massachusetts in Amherst, and Virginia Tech in Blacksburg, and has held visiting positions at the University of Tokyo, Japan, the Universities of Freiburg and Potsdam in Germany, the Indian Institutes of Technology, and as a Fulbright scholar at the University Polytechnic of Catalonia in Barcelona, Spain. His technical interests span all aspects of VLSI technology, in particular integrated circuit test and reliability. He has published over three hundred research papers and holds international patents that have been licensed to industry. He has served as a consultant to several semiconductor and EDA companies, including as an expert witness for major patent litigation cases. He has had leadership roles as General Chair/Co-Chair/Program Chair for dozens of international VLSI design and test conferences. He served two terms (2007-11) as Chair of the IEEE Test Technology Technical Council (TTTC), and (2011-15) on the Board of Governors of the IEEE Council on Design Automation (CEDA). Singh received his B.Tech from IIT Kanpur, and the M.S. and Ph.D. from Virginia Tech, all in Electrical Engineering. He is a Life Fellow of IEEE.\N \N \N\N
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Moderator: Stefano di Carlo
Affiliation: Politecnico di Torino (IT)
Silent Data Corruption from Timing Marginalities Due to Process Variations
Author: Adit D. Singh
Affiliation: Auburn University (US)
We make the case, supported by recently published industrial data, that many of the hard to detect failures that escape post manufacturing tests and contribute to silent data corruption are timing failures resulting from significant increases in the delay of random circuit paths caused by manufacturing process variations. However, these are challenging to target at test because high coverage scan path delay tests are impractical. This research is investigating the characteristics of extreme statistical outlier slow paths in circuits with the goal of finding alternate test methods to detect and screen them out. We are particularly focused on low voltage operation because circuit delays due to process variations are greatly accentuated in that environment. A significant observation from this study is that delay increases from variability are not uniformly distributed among the gates in a potentially failing slow path. Instead, most of the delay increase is concentrated in a single gate. This suggests that node oriented TDF timing tests may also detect many of the timing failures caused by process variations. We show how the test voltage and clock timing of the applied TDF scan tests can be optimized to enhance the likelihood of detection of these marginal timing parts.
Adit Singh is Godbold Endowed Chair and Professor of Electrical and Computer Engineering at Auburn University, USA. He earlier served on the faculties of the University of Massachusetts in Amherst, and Virginia Tech in Blacksburg, and has held visiting positions at the University of Tokyo, Japan, the Universities of Freiburg and Potsdam in Germany, the Indian Institutes of Technology, and as a Fulbright scholar at the University Polytechnic of Catalonia in Barcelona, Spain. His technical interests span all aspects of VLSI technology, in particular integrated circuit test and reliability. He has published over three hundred research papers and holds international patents that have been licensed to industry. He has served as a consultant to several semiconductor and EDA companies, including as an expert witness for major patent litigation cases. He has had leadership roles as General Chair/Co-Chair/Program Chair for dozens of international VLSI design and test conferences. He served two terms (2007-11) as Chair of the IEEE Test Technology Technical Council (TTTC), and (2011-15) on the Board of Governors of the IEEE Council on Design Automation (CEDA). Singh received his B.Tech from IIT Kanpur, and the M.S. and Ph.D. from Virginia Tech, all in Electrical Engineering. He is a Life Fellow of IEEE.
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