On Parametrized Virtual Testing and Simulation of Verilog-AMS Behavioral Models
Affiliations: 1 University of Stuttgart Stuttgart (DE), 2 Advantest Europe GmbH (DE)
The traditional development of test programs for Analog Mixed Signal (AMS) circuits is both time-consuming and cost-intensive, with validation of only physically available chips. The testing is conducted by providing a set of test inputs. The type of inputs and the optimal sequence is highly dependent on the Circuit Under Test (CUT) and therefore requires expert knowledge. Hence, a desirable solution is a virtual test framework that enables pre-tapeout testing and aids the design phase with early feedback regarding the fulfillment of circuit specifications. In this extended abstract, we introduce a concept of a new simulative approach based on behavioral models featuring parameterizable fault characteristics in Verilog-AMS models. The proposed framework also encompasses models of tester instruments and signal transmission paths. Preliminary simulation results are provided showcasing the feasibility of this approach.
Thorben Schey received the M.Sc. degree with distinction in electrical engineering and information technology from the University of Stuttgart, Germany, in 2023, where he is currently pursuing the Ph.D. degree at the Institute of Industrial Automation and Software Engineering (IAS). He is also a Doctoral Researcher at IAS. His research interests include virtual testing and behavioral models for chip test.
Techniques for Building Reliable and Energy-Efficient Hardware Accelerators for Dynamic Deep Neural Networks
Affiliation: Tallinn University of Technology (EE)
This paper explores the design and integration of Dynamic Deep Neural Networks (D2NN or DynNN) intohardware accelerators to improve reliability while minimizing energy consumption. To achieve optimal performance, we study the decision-making sub-networks, early-exiting techniques, and pruning strategies. Considering the increasing transistor density in AI chips, we address the critical issue of D2NN vulnerability toradiation-induced soft errors and adversarial attacks, proposing architectural modifications and validation techniques to ensure the integrity of these accelerators for safety-critical applications.
I am a first-year Ph.D. student at Tallinn University of Technology, studying under the supervision of Prof. Dr. Maksim Jenihhin. My research focuses on the Reliability of Dynamic Neural Network (D2NN) Hardware accelerators. Additionally, I am a full-time DFX Pre-Silicon Validation Engineer at Intel. I develop System Verilog-based UVM test cases for IP and sub-system validation. Furthermore, I conduct digital fault grading of HVM test cases before delivering them to post-silicon customers.
Design of efficient Hardware Inference Engines for Edge AI
Affiliation: Tallinn University of Technology (EE)
Very recently, the rampant fusion of AI algorithms with computing hardware for edge AI devices has raised theconcerns for designing the delay and power-area efficient, and reliable hardware architectures. The imperative motivation behind this work is to bridge the gap between increasing computational demands and the limitations of AI hardware. This PhD work aims to introduce novel approaches for advanced and optimized hardware architectures to improve the performance parameters of delay, power and area for efficient AI hardware.
Ahsan Rafiq, is an early stage researcher in Tallinn University of Technology since October 2023. He did his master thesis research in high speed and low power digital circuits and systems’ design. Therefore, it was my motivation earlier to work in this field due to my expertise and growing research in this field of digital system design. So, I have decided to pursue my career further in research and academia. This is my motivation for PhD.
Deploying Compact and Dependable DNNs in Safety-critical Applications
Affiliations: 1 Ecole Centrale de Lyon (FR), 2 Univ. Grenoble Alpes,CNRS,Grenoble (FR)
This work aims at developing generation methods for compacting Deep Neural Networks (DNNs) to fit low-power micro controllers used in safety and mission-critical applications. The objective is to implement a Network Architecture Search (NAS) framework to identify the best DNN implementation for a set of application and system requirements, accounting for different embedded computers. To achieve this objective, weintend to develop a bottom up approach in which we characterize DNN components (e.g., convolutional layer, fully connected layer) in terms of energy efficiency and reliability. In this paper, we target the reliability characterization of DNNs through radiation experiments. Thermal neutron beaming will reveal hardware error models that will be used to simulate assorted hardening techniques. After observing and comparing several DNN algo rithms, on different embedded hardware architectures, these combinations will be validated on new radiation tests. It is expected to understand specific weaknesses of each system and which hardening solutions can circumvent radiation effects on each hardware/software combination.
Leonardo Alexandrino is an Aerospace Engineer and Mechatronics Technician from Brazil, who started his PhD this year at Lyon Institute of Nanotechnology at Ecole Centrale de Lyon, in France. His topics of research are: Deep Neural Networks, Embedded Systems, Automation, Nanosatellites, Test and Systems Engineering.
Towards Ultra-Reliable Automotive Systems-on-Chip
Affiliation: Politecnico di Torino (IT)
Embedded nano-electronic systems are becoming more prevalent in people’s daily lives. As a result, chip andembedded system manufacturing has become increasingly complicated and huge in recent years. As a result, manufacturers are faced with significant complexity in testing their embedded systems to ensure the needed reliability for safety-critical fields. This Ph.D. thesis aims at introducing novel testing approachesto face the complexity of new and more complex industrial case studies.
Giusy Iaria is a Ph.D. student in her third year inComputer and Control Engineering at Polytechnicof Turin, Italy. She is part of the CAD & Reliabilityresearch group with a strong focus on Embeddedelectronics testing. After a research fellowship onthe reliability of safety-critical devices, she started her Ph.D. to find strategies and evaluation methods to reach ultra-reliability in Automotive Systems-on-Chip.
System-Level Test techniques for Automotive SoCs
Affiliation: Politecnico di Torino (IT)
No Abstract
Francesco Angione is a Computer Engineer with an M.Sc., Embedded Systems track, obtained from Politecnico di Torino in 2020. Currently, he is working towards a Ph.D. on "System-Level-Test techniques for Automotive SoCs" at Politecnico di Torino in the CAD & Reliability group. His main interests are real-time operating systems, computer architectures, and their dependability.
Leveraging FPGAs for Faster and Less Memory-Demanding Burn-In Testing
Affiliation: Politecnico di Torino (IT)
In recent years, we have seen exponential growth in the complexity of SoCs. More powerful and efficient chips have been developed and integrated into more complex and increasingly interconnected environments. However, this increase in complexity has translated into an increase in the difficulty of testing the correct functioning of these chips. Techniques used in the past have proven insufficient to cope with this increase in complexity. Today, more than ever, it is necessary to find new testing techniques or modify existing techniques to guarantee the correct functioning of the chips once they have passed the testing phase. In this article, we will discuss how, through a board equipped with an FPGA, it is possible to implement a fast burn-in test to ensure the quality of a device, which was carried out using an STMicroelectronics chip from the SPC58 family.
Tommaso Foscale completed his bachelor studies and Master's on Computer Science at Politecnico di Torino, Turin, in 2019 and 2021. He is on the second year of Ph.D. at Politecnico di Torino. His research interests include wafer testing, machine learning and software programming.
Exploiting The Connectivity Metric In Test Programs Generation
Affiliation: Politecnico di Torino (IT)
The escalating complexity of today’s systems-on-chip (SoCs) poses an increasing challenge to verifying their full functionality. Modern applications of such devices often require stringent safety standards. To uphold such a rigorous level of quality, the need for lengthy procedures that ensure high fault coverage has become increasingly crucial. Multiple techniques to speed up this process have been proposed over the years but, in this article, we will focus on the connectivity metric proposed by Francesco Angione et al. We will discuss the possibility of using the proposed metric to shorten the time required to generate a test program. We will exploit a well-known test-program generation tool, known as microGP, evolving an initial population focusing first on the connectivity metric to quickly reach a population of individuals with reasonable features before switching to the traditional fault simulation metric.
Lorenzo Cardone is PhD student at Politecnico di Torino, where he graduated in 2021 in Computer Science. His main research topics are software parallelization and optimization, and he has recently started working in the field of hardware testing.
Enhancing Assertion-Based Verification in Hardware Designs through Data Mining
Affiliation: Tallinn University of Technology (EE)
In the realm of assertion-based verification, several assertion miners automatically generate assertions for verifying hardware designs. Despite their promising features, these min- ers suffer from drawbacks such as high execution time and low mutant detection coverage. In this research, we introduce a data mining-based assertion miner to automatically mine assertions. Our experiments show that our assertion miner generates fewer but more accurate assertions compared to other miners.
Mohammad Reza Heidari Iman is a Ph.D. candidate in the Department of Computer Systems at Tallinn University of Technology, Estonia. His research interests include verification, assertion-based verification, and security verification in embedded systems. He also explores the application of data mining in hardware verification.
Manufacturing and In-Field Testing Techniques
Affiliation: Politecnico di Torino (IT)
The automotive industry is currently undergoing a period of rapid technological advancement. This is evidenced by the significant shift towards fully electric vehicles equipped with complex integrated circuits. This surge in technological complexity necessitates the implementation of more rigorous and adaptable testing methodologies throughout entire device lifecycle, encompassing all stages from initial manufacturing to final disposal. While traditional testing approaches still hold value, it is crucial to explore and develop novel techniques to effectively navigate this rapidly evolving landscape and ensure the safety and functionality of these increasingly sophisticated devices.
G. Filipponi is a second-year Ph.D student in Computer and Control Engineering at Politecnico di Torino. He is part of the Electronic CAD & Reliability group, with a focus on Embedded electronics testing. His main field of research regards ultra reliability for in-field Automotive SoC, specifically exploiting the Logic BIST.
Time Guarantee and Reliable Execution for Safety-Critical Real-Time Systems
Affiliation: University of Rennes (FR)
Safety-critical real-time embedded systems must guarantee both reliable and in-time execution. The increasing complexity of embedded systems and the reduction in technology size make modern processors more vulnerable to faults, especially in multicore systems, where it’s difficult to predict the timing behavior due to numerous interference. Faults impact not only the functional correctness of the application but also the timing correctness, which is paramount for safety-critical systems. The goal is to propose means to evaluate systems in the presence of faults and propose techniques that mitigate the errors to allow a safe execution. For the first step discussed in the following, we enhance vulnerability analysis to include functional and timing correctness, show that faults impact Worst-Case Execution Time (WCET) estimations, and propose a fault tolerance technique.
Pegdwende Romaric NIKIEMA is a 2nd year Ph.D student at Université de Rennes, France. He received his B.S. degree in Electronic Electrotechnic and Control System from the Université Aube Nouvelle, Burkina Faso in 2020, his M.S. degree in Wireless Embedded Technology from the Nantes Université, France in 2022. His research interests include computer architectures, Real-time and dependable embedded systems.
Irradiation Tests: Deriving Memory Design Parameters
Affiliation: Politecnico di Torino (IT)
This paper introduces a new method to derive architectural details from embedded System-on-Chip(SoC) memories. This method can extract memory design configurations (MDCs) such as mirroring, and scrambling utilizing Multiple Cell Upsets (MCUs) generated through a single irradiation test. Discovering the correct MDC corroborates the proposed method although, this method may find redundant MDCs alongside the correct MDC. The number of these redundant MDCs decreased with the increment of the MCUs. This number decreased to an average of 2 possible MDCs when considering 100 MCUs.
Nima Kolahimahmoudi received his master’s in Electronic Engineering at the Polytechnic of Turin in 2022. Currently, he is a Ph.D. student in the Department of Control and Computer Engineering in the CAD and Reliability group under the supervision of Professor Paolo Bernardi. Mainly, his research targets the test and reliability of Automotive Systems-on-Chips, including analog and mixed-signal circuits and embedded memories.
A Novel Machine Learning-based Fault Shape Classification for Memories Embedded In Automotive Systems-on-Chip
Affiliation: Politecnico di Torino (IT)
A significant percentage of modern Automotive System-on-Chip dies is occupied by embedded memories. Embedded memories have thus a high impact on the yield of these devices, and their testing and reliable operations are then key priorities for the manufacturers. Embedded memories are tested with a complete suite of tests that verify the correct behavior of the bit cells in various conditions such as supply voltage, operation frequency, temperature, etc. All these tests generate huge quantities of data that are difficult to analyze and to elaborate in an easily understandable form. A useful approach is to divide the failures based on their fault shapes. For example, a series of adjacent bitlines is probably related to a sense amplifier failure, or a series of adjacent wordlines is probably related to a failing minisector. Heuristic programs to recognize these shapes exist, but they are slow, not flexible, and prone to mistakes. In this work, we propose a new shape analysis solution that uses machine learning to recognize fault shapes faster and more reliably. To reach our goals, we trained a convolutional neural network (CNN) called ResNet18. This net is very famous in the literature for having high performance and being relatively lightweight. It takes its name from the 18 layers that compose it and accepts image tiles of 224x224 pixels and outputs the label of the recognized fault shape. The complete flow includes a preprocessing phase that prepares the input for the neural network and a post-processing phase that combines the output of the neural network to recognize bigger shapes. Experimental results on an Automotive-grade Infineon SoC show the validity of the approach, which correctly recognizes 97.9% of the failure on a set of 8000 failing segments.
Giorgio Insinga received his master's degree in Electronics Engineering at Politecnico di Torino in 2021. He is a Ph.D. student at Politecnico di Torino under the supervision of professor Paolo Bernardi. His primary research focuses on the test and reliability of Automotive Systems-on-Chip and their embedded memories.
Exploring Side Channel Attacks on Cutting-Edge Adder-Free SRAM CIM
Affiliation: Delft University of Technology (NL)
A novel adder-free SRAM-based Computation-in-Memory (CIM) accelerator for Binary Neural Networks (BNNs) is susceptible to power side-channel attacks. This work proposes a framework to exploit the CIM periphery’s power signature to reverse-engineer SRAM cell weights. The methodology isolates the counter’s power signature, segments the power trace, and profiles these segments to identify weight values. Initial findings based on power profile analysis demonstrate the feasibility of weight information extraction. This work highlights the importance of security in CIM design and motivates research on countermeasures like masking or obfuscation to mitigate power side-channel vulnerabilities. Our contribution is a novel attack approach for digital CIM devices, paving the way for future research in securing these systems.
Fouwad Mir is a Ph.D. candidate in Computer Engineering at the faculty of Electrical Engineering, Mathematics and Computer Science (EEMCS), Delft University of Technology (TU-Delft). His research focuses on hardware security for novel computer architectures and neural network accelerators. He is enthusiastic about exploring hardware security vulnerabilities in digital and mixed-signal designs, aiming to develop mitigation strategies for robust and secure hardware.
Online Detection of Unique Faults in RRAMs
Affiliations: 1 Delft University of Technology (NL), 2 Aix-Marseille University (FR), 3 CognitiveIC (NL)
Due to the immature manufacturing process, Resistive Random Access Memories (RRAMs) are prone to exhibitnew failure mechanisms and faults, which should be efficiently detected for high-volume production. Those unique faults are hard to detect but require specific Design-for-Test (DfT) circuit design. This paper proposes a DfT based on a parallel-reference write circuit that can detect all RRAM array faults during diagnosis, production testing, and its application in the field.
Hanzhi Xun received the B.Sc. and M.Eng. degrees from Xidian University, Xi'an, China, in 2018 and 2021, respectively. He received another M.Eng. degree form Waseda University, Kitakyushu, Japan, in 2021. He is currently working toward the Ph.D. degree at the Computer Engineering Laboratory, Delft University of Technology, Delft, The Netherlands. His research interests focus on device modeling, test, and reliability of Resistive RAMs.
Reliability Assessment and Optimization of Dynamic DNNs for Edge Accelerators
Affiliation: University of Cyprus (CY)
The urge to deploy Machine Learning (ML) algo- rithms for inference on edge devices, has created the need for efficient, resource-constrained and dependable hardware, that can be utilized according to the constraints of the underlying hardware as well as those imposed by the running applications. Recently, various types of dynamic deep neural networks have been introduced, mainly for the purpose of optimizing inference performance for real-time response systems. Such edge-based systems are often resource-constrained and are deployed in various safety-critical and/or harsh environments. Therefore, these systems have increased needs in reliability, while at the same time struggle to satisfy performance and energy requirements. This thesis will first investigate the vulnerability assessment of various dynamic deep neural networks, in order to better understand the impact of these performance optimizations on the overall reliability of the networks. Consequently, the thesis will propose various approaches to co-optimize the network design based on both performance and reliability targets. The proposed approaches will be evaluated within a newly developed simulation framework which allows for efficient yet accurate vulnerability analysis, as it considers hardware-aware software fault models.
Georgios Konstantinidis received his BSc degree in Electrical and Electronic Engineering from the Department of Electrical and Computer Engineering at the University of Cyprus and his MSc degree in Mechatronics from the department of Mechanical Engineering at the University of Leeds. He is currently a PhD student. His research interests include Machine Learning, Embedded Systems, Forecasting Algorithms and ML Accelerators.
Pre-Silicon Fuzzing of RISC-V Hardware Components and their Interactions
Affiliation: Delft University of Technology (NL)
In recent years, processor microarchitectures have shown both functional and security issues. Current mitigation-focused research centers around undirected testing of processors, i.e. hardware or processor fuzz testing. More recent promising studies focus on using test programs as fuzz inputs. Cascade, which is the state-of-the-art in these test program focused tools, uses a loosely integrated collection of existing tools. This severely limits what intricate behaviors and chip-component interactions it can test and the speed at which it can generate test programs. We propose a set of tightly integrated tools that allow for the real-time program generation. These tools allow for automation in the behavioral verification and security analysis of intricate interactions between chip-components.
Gijs Burghoorn finished a BSc. Computer Science at Leiden University in the Netherlands. Afterwards, he went to Grenoble in France and got a MSc. in Informatics and Cybersecurity. Here, he performed research into Hardware Security, Side-Channel Analysis and Fault Injection. Afterwards, he started his PhD at the TU Delft in the Netherlands.