Download the complete pdf version of the call for papers here.


Each submitted paper should be a complete PDF manuscript, up to six (6) pages (inclusive of all figures, tables, and bibliography) in a standard IEEE format: A4 pages, two columns, single spaced, 10 points Times New Roman font. IEEE template that can be found [here]. Papers not compliant with the IEEE template or exceeding the page limit will be returned without review!

ETS implements single-blind review process (i.e. the authors do not know who the reviewers are, the reviewers know who the authors are). Therefore, submissions should not be anonymized.

Papers identified as multiple submissions with respect to other conferences and/or journals will also be rejected. Authors are expected to follow the IEEE Submission and Peer Review Policies, including the latest Policy on plagiarism as well as the Guidelines for AI generated text, all of which can be found [here]

A submission of a scientific paper is considered as a commitment that, upon acceptance, authors will submit their camera-ready version for inclusion in the formal proceedings and will present the paper (or the poster) at the symposium. ETS reserves the right to remove from IEEE Xplore papers and posters that have not been presented at the symposium.

Key Dates

Submission of title, abstract, authors: 8 December 2023 15 December 2023 (firm)
Final Paper Submission: 16 December 2023 22 December  2023 24:00 AoE (firm)
Question to Authors (optional): 3 February 2024, 1pm CET
Authors’ Response (optional): 6 February 2024, 1pm CET
Authors may receive a question to clarify certain points in their paper, after reviews will be submitted. This is not an official rebuttal process, response is optional but highly recommended. Questions will be sent by Feb 3 and brief responses (max 500 words) should be submitted by Feb 6.

Author Notification: 16 February 2024
Camera-ready Submission: 15 March 2024
Author Registration: 31 March 2024

Topic Areas for Submission

Below you can find the list of the topics (not limited to) for ETS'24.

  • T1 - Dependable AI and AI for Testing
    AI/ML is thriving across numerous applications and we are only at the beginning of the revolution. Not surprisingly, AI/ML is gaining popularity for solving dependability and testing problems for ICs. In parallel, we need to address the problem of dependability and testing of emerging AI hardware accelerators. This topic considers fault modeling, structural testing, functional testing,  on-line test, reliability, fault tolerance and functional safety, all for AI/ML hardware. Also, it considers the application of AI/ML in IC manufacturing testing, reliability, fault diagnosis and failure analysis, on-line testing, anomaly detection, and functional safety.
  • T2 - Functional Safety and Reliability
    Functional safety (FuSa) and reliability are essential aspects of modern electronic systems, especially in domains such as automotive, aerospace, medical, and industrial. These systems require advanced design and test methods to ensure their correct, secure, and dependable operation in the field. Topics of interest: dependability, defense mechanisms, design for reliability, fault injection, yield analysis and enhancement safety.
  • T3 - Emerging Technologies and Architectures
    Until now, the innovation of computing devices has relied on incremental improvements in technology and architecture. However, it has become apparent that a paradigm shift is needed to enable new performance breakthroughs, such as novel processing and computing paradigms and non-CMOS-based technology. This topic considers test and reliability methods for: approximate circuits; in-memory computing; neuromorphic architectures; photonic devices and architectures; quantum and reversible circuits and architectures.
  • T4 - Security and Trust
    The widespread use of electronic devices in critical and multitenant applications brings as a major requirement the assurance of security and trust. However, with the growing complexity of the electronic systems design, the risk of malware infections, vulnerabilities and Trojans introduced at design time increases significantly. Proper methods that address security and trust issues by design as well as innovative solutions for thevarious security aspects of electronic devices are mandatory. This topic considers: methods, tools and use cases on design for security; test methods for secure systems (e.g., cryptographic primitives, RNGs, PUFs); test infrastructure for secure devices; secure design methods against physical attacks (e.g., fault attacks, side channels); security issues in test (attacks and countermeasures); trusted hardware design and manufacturing; hardware Trojans, detection and countermeasures.
  • T5 - Test and Reliability for Analog, Mixed-Signal, and RF
    Despite many years of research efforts, Analog, Mixed-Signal and RF test remains highly circuit-specific. The complexity of the problem stems from both the diversity of performance specifications and the sensitivity to any change in the signal path. However, AMS-RF researchers are undeterred, and this topic will bring together their latest advances. Topics include test and reliability in: analogue and mixed-signal circuits, high-speed digital circuits, MEMS sensors and RF circuits.
  • T6 - DfT and Test Access Standards
    Design for Testability (DFT) solutions are needed to provide the circuit access required to achieve ultra-low defect levels at manufacturing and enable the detection of new failures later in the field. Updated standards for secure and effective test are also needed to ensure interoperability. This topic considers all aspects of design for test, including built-in self-test,  scan design, online monitoring, and test access standards, for circuits and system architectures such as NoC, SoC, and 3-D test and chiplets.
  • T7 - Validation, Verification, Debug and Diagnosis
    Methodologies and tools for validation, verification, debug and diagnosis of ICs, embedded hardware and software, and cyber-physical systems, by exploiting formal, semi-formal and dynamic approaches, with or without the use of artificial intelligence. Topics include: testbench and assertion generation and qualification; fault/mutant modeling and simulation; checker synthesis and optimization; multi-domain and mixed-critical validation and verification techniques; pre- and post-silicon diagnosis and debugging solutions; security verification and detection of vulnerabilities; formal verification methods and core algorithm techniques supporting formal verification; accelaration-driven and emulation-based approaches for verification and diagnosis; verification and validation of safety mechanisms.
  • T8 - Test Generation, Fault Simulation, Fault Tolerance, Application and Evaluation
    Test generation and fault simulation techniques across various abstraction levels, e.g. cell-aware, gate-level, system-level, as well as for different fault models, e.g. traditional, defect-oriented and transient. Fault tolerance techniques such as online testing. Application and assessment results for real systems regarding performance and reliability. Sub-topics considered include: fault tolerance; on-line testing; self-repair; adaptive testing; ATPG; defect-oriented testing; fault simulation; transient faults; system-level test; solving techniques; delay test; efficiency/effectiveness; reliability; feedback & iterative improvement.

Please refer to the program committee page for the topic chairs

Submission Website

Click here to submit your paper. Only electronic submission of PDF files via the paper submission page are accepted.


ETS'24 will produce electronic formal proceedings - with ISBN number, and to be indexed in the IEEE Xplore digital library and other bibliographical search engines. Scientific papers can be accepted for:

  • oral presentation: you will be asked to prepare a final 6-page manuscript for inclusion in the formal proceedings;
  • poster presentation: in this case a 4-page paper will be included in the formal proceedings.

The formal proceedings will contain the PDF files of all accepted papers of accepted posters. 

The Best Paper Award of ETS’24 will be presented at ETS’25.

Contact Information

For more information, please contact the Program Chair This email address is being protected from spambots. You need JavaScript enabled to view it..