Oral Presentations

17 Polynomial Formal Verification of Approximate Adders with Constant Cutwidth
18 Test Compression for Neuromorphic Chips
19 Characterization of Ultra-low random jitter reduction methods up to 36 GHz
26 Power Analysis Attack Against post-SAT Logic Locking schemes
30 Test and Repair Improvements for UCIe
36 Testing Spintronics Implemented Monte Carlo Dropout-Based Bayesian Neural
38 Design-for-Test for Intermittent Faults in STT-MRAMs
45 Time and Space Optimized Storage-based BIST under Multiple Voltages and Process Variations
50 IEEE 1838 compliant scan encryption and integrity for 2.5/3D ICs
55 A Novel Power Analysis Attack against CRYSTALS-Dilithium Implementation
62 Fault Sensitivity Analysis of Printed Bespoke Multilayer Perceptron Classifiers
64 Detection of Stealthy Bitstreams in Cloud FPGAs using Graph Convolutional Networks
66 Cross-Layer Reliability Analysis of NVDLA Accelerators: Exploring the Configuration Space
67 Hierarchical Fault Simulation for Mixed-Signal Circuits Using Template Based Fault Response Modeling
75 CGAN-based Automated Fault Injection
76 On-chip Built-In Self-Calibration of Thermal variations for Mixed-Signal In-Memory Computing
91 Counteracting Rowhammer by Data Alternation
96 Degradation Monitoring Through Software-controlled On-chip Sensors for RISC-V
117 Faulty Function Extraction for Defective Circuits

Poster Presentations

15 Formal Resilience Metric Characterization in Complex Digital Systems
22 Analyzing the Structural and Operational Impact of Hardware Faults in Floating-Point and Posit Arithmetic Cores for CNN Operations
24 Hardening Bus-Encoders with Power-Aware Single Error Correcting Codes
35 MBIST-based weak bit screening method for embedded MRAM
43 GNN-Based INC and IVC Co-optimization for Aging Mitigation
53 Error Detection and Correction Codes for Safe In-Memory Computations
56 A Fully Pipelined High-Performance Elliptic Curve Cryptography Processor for NIST P-256
72 Parallel-Check Trimming Test Approach for Selecting the Reference Resistance of STT-MRAMs
82 Analog Defect Simulation Efficiency Improvement based on AMS Verification Analysis
85 A Multi-Objective Evolutionary Approach for Test Network Design
89 AdAM: Adaptive Fault-Tolerant Approximate Multiplier for Edge DNN Accelerators
92 Relation Coverage: A new Paradigm for Hardware/Software Testing
98 Modeling Thermal Effects For Biasing PUFs
99 Post-Manufacture Criticality-Aware Gain Tuning of Timing Encoded Spiking Neural Networks for Yield Recovery
100 Extracting Weights of CIM-Based Neural Networks Through Power Analysis on Adder-Tree
106 Training Large Language Models for System-Level Test Program Generation Targeting Non-functional Properties
108 Optimizing System-Level Test Program Generation via Genetic Programming
111 Scan Design Using Unsupervised Machine Learning to Reduce Functional Timing and Area Imact
114 Assessing the Effectiveness of Software-Based Self-Test Programs for Static Cell-Aware Test
116 AMS Test Stimulus Generation and Response Analysis Using Hyperdimensional Clustering: Minimizing Misclassification Rate
121 Transcoders: A Better Alternative to Denoising Autoencoders