Workshop Program

Welcome Address

General Chair: Erik Jan Marinissen – imec (BE)
Program Chair: Martin Keim – Siemens Digital Industries Software (US)

Keynote Address: Stepping up to the Chiplet (Interconnect) Test Challenge

Jeff Rearick – AMD (USA)

Abstract: Through some amazing advances in packaging technology, we’ve entered the “More-than-Moore” era where the long-predicted slowdown in chip density and performance not only didn’t happen but went the other direction: assembling multiple chiplets into a single package has enabled gigantic transistor counts and staggering power levels that the test community must grapple with in new ways. This talk will review the latest technology trends (with examples from the industry), touch on some of the test challenges that come along with the entire chiplet ecosystem, then focus on the unique challenges of chiplet-to-chiplet interconnect test and repair. Topics will include 2.5D vs. 3D testing, soft vs. hard repair, standards, fault models, data volume, test access, partial assembly test, thermal management and power delivery, among others. The inescapable conclusion is that there is a substantial amount of hard work to do and that we test engineers will be in the spotlight to get it done.

Illuminating Blind Spots in Chiplet Interconnect Testing

Nir Sever* – Proteantecs (USA)

DfT Standards Lessons for IEEE Std P3405

Martin Keim* – Siemens Digital Industries Software (US)

Panel on Session 1

All speakers

Welcome Reception

End of Day 1

Physical Aware Interconnect Testing and Repairing of Chiplets

Tuanhui Xu* – HiSilicon (CN)

An Exploration of Error Correction Approaches for Chiplet Interfaces

Antoine Rouget* – ST Microelectronics (FR)

Insights on Chip Repair Techniques from Existing Industrial Solutions

Adrian Evans – CEA/LIST (FR)

Panel on Session 2

All speakers

Coffee/Tea Break

Interconnects in 3D Technology

Jaber Derakhshandeh* – imec (BE)

The Reliability Imperative: Navigating Challenges in 3D IC Integration

Stéphane Moureau* – CEA/LIST (FR)

Streamlining Silicon Photonic Chiplet Testing

Quan Yuan* – FormFactor (USA)

Test and Repair of Small Bridging Defects Occurring to TSVs in a 3D-DRAM Using Enhanced Pulse-Vanishing Test

Shi-Yu Huang* - National Tsing-Hua University (TW)

Panel on Session 3

All speakers

Lunch

Repair Logic Description Language

Po-Yao Chuang*, Erik Jan Marinissen – imec (BE)

Examples of EDA Tools Based on a Standardized Repair Description Language

Tsung-Hsuan Wang* – imec/NYCU (BE/TW)

Po-Yao Chuang, Erik Jan Marinissen – imec (BE)

IEEE Std P3405 from an EDA Vendor Point of View

Martin Keim*, Anshuman Chandra – Siemens EDA (USA)

Panel on Session 4

All speakers

IEEE Std P3405 Overview

Sreejit Chakravarty – Ampere Computing (USA)

Abstract: TBW

Farewell

General Chair: Erik Jan Marinissen – imec (BE)

End of Day 2