Coffee Break - PhD Forum 2 and McCluskey Posters
Description
Affiliation: University of Rennes (FR)
Enhancing Assertion-Based Verification in Hardware Designs through Data Mining
Affiliation: Tallinn University of Technology (EE)
In the realm of assertion-based verification, several assertion miners automatically generate assertions for verifying hardware designs. Despite their promising features, these min- ers suffer from drawbacks such as high execution time and low mutant detection coverage. In this research, we introduce a data mining-based assertion miner to automatically mine assertions. Our experiments show that our assertion miner generates fewer but more accurate assertions compared to other miners.
Mohammad Reza Heidari Iman is a Ph.D. candidate in the Department of Computer Systems at Tallinn University of Technology, Estonia. His research interests include verification, assertion-based verification, and security verification in embedded systems. He also explores the application of data mining in hardware verification.
Manufacturing and In-Field Testing Techniques
Affiliation: Politecnico di Torino (IT)
The automotive industry is currently undergoing a period of rapid technological advancement. This is evidenced by the significant shift towards fully electric vehicles equipped with complex integrated circuits. This surge in technological complexity necessitates the implementation of more rigorous and adaptable testing methodologies throughout entire device lifecycle, encompassing all stages from initial manufacturing to final disposal. While traditional testing approaches still hold value, it is crucial to explore and develop novel techniques to effectively navigate this rapidly evolving landscape and ensure the safety and functionality of these increasingly sophisticated devices.
G. Filipponi is a second-year Ph.D student in Computer and Control Engineering at Politecnico di Torino. He is part of the Electronic CAD & Reliability group, with a focus on Embedded electronics testing. His main field of research regards ultra reliability for in-field Automotive SoC, specifically exploiting the Logic BIST.
Time Guarantee and Reliable Execution for Safety-Critical Real-Time Systems
Affiliation: University of Rennes (FR)
Safety-critical real-time embedded systems must guarantee both reliable and in-time execution. The increasing complexity of embedded systems and the reduction in technology size make modern processors more vulnerable to faults, especially in multicore systems, where it’s difficult to predict the timing behavior due to numerous interference. Faults impact not only the functional correctness of the application but also the timing correctness, which is paramount for safety-critical systems. The goal is to propose means to evaluate systems in the presence of faults and propose techniques that mitigate the errors to allow a safe execution. For the first step discussed in the following, we enhance vulnerability analysis to include functional and timing correctness, show that faults impact Worst-Case Execution Time (WCET) estimations, and propose a fault tolerance technique.
Pegdwende Romaric NIKIEMA is a 2nd year Ph.D student at Université de Rennes, France. He received his B.S. degree in Electronic Electrotechnic and Control System from the Université Aube Nouvelle, Burkina Faso in 2020, his M.S. degree in Wireless Embedded Technology from the Nantes Université, France in 2022. His research interests include computer architectures, Real-time and dependable embedded systems.
Irradiation Tests: Deriving Memory Design Parameters
Affiliation: Politecnico di Torino (IT)
This paper introduces a new method to derive architectural details from embedded System-on-Chip(SoC) memories. This method can extract memory design configurations (MDCs) such as mirroring, and scrambling utilizing Multiple Cell Upsets (MCUs) generated through a single irradiation test. Discovering the correct MDC corroborates the proposed method although, this method may find redundant MDCs alongside the correct MDC. The number of these redundant MDCs decreased with the increment of the MCUs. This number decreased to an average of 2 possible MDCs when considering 100 MCUs.
Nima Kolahimahmoudi received his master’s in Electronic Engineering at the Polytechnic of Turin in 2022. Currently, he is a Ph.D. student in the Department of Control and Computer Engineering in the CAD and Reliability group under the supervision of Professor Paolo Bernardi. Mainly, his research targets the test and reliability of Automotive Systems-on-Chips, including analog and mixed-signal circuits and embedded memories.
A Novel Machine Learning-based Fault Shape Classification for Memories Embedded In Automotive Systems-on-Chip
Affiliation: Politecnico di Torino (IT)
A significant percentage of modern Automotive System-on-Chip dies is occupied by embedded memories. Embedded memories have thus a high impact on the yield of these devices, and their testing and reliable operations are then key priorities for the manufacturers. Embedded memories are tested with a complete suite of tests that verify the correct behavior of the bit cells in various conditions such as supply voltage, operation frequency, temperature, etc. All these tests generate huge quantities of data that are difficult to analyze and to elaborate in an easily understandable form. A useful approach is to divide the failures based on their fault shapes. For example, a series of adjacent bitlines is probably related to a sense amplifier failure, or a series of adjacent wordlines is probably related to a failing minisector. Heuristic programs to recognize these shapes exist, but they are slow, not flexible, and prone to mistakes. In this work, we propose a new shape analysis solution that uses machine learning to recognize fault shapes faster and more reliably. To reach our goals, we trained a convolutional neural network (CNN) called ResNet18. This net is very famous in the literature for having high performance and being relatively lightweight. It takes its name from the 18 layers that compose it and accepts image tiles of 224x224 pixels and outputs the label of the recognized fault shape. The complete flow includes a preprocessing phase that prepares the input for the neural network and a post-processing phase that combines the output of the neural network to recognize bigger shapes. Experimental results on an Automotive-grade Infineon SoC show the validity of the approach, which correctly recognizes 97.9% of the failure on a set of 8000 failing segments.
Giorgio Insinga received his master's degree in Electronics Engineering at Politecnico di Torino in 2021. He is a Ph.D. student at Politecnico di Torino under the supervision of professor Paolo Bernardi. His primary research focuses on the test and reliability of Automotive Systems-on-Chip and their embedded memories.
Exploring Side Channel Attacks on Cutting-Edge Adder-Free SRAM CIM
Affiliation: Delft University of Technology (NL)
A novel adder-free SRAM-based Computation-in-Memory (CIM) accelerator for Binary Neural Networks (BNNs) is susceptible to power side-channel attacks. This work proposes a framework to exploit the CIM periphery’s power signature to reverse-engineer SRAM cell weights. The methodology isolates the counter’s power signature, segments the power trace, and profiles these segments to identify weight values. Initial findings based on power profile analysis demonstrate the feasibility of weight information extraction. This work highlights the importance of security in CIM design and motivates research on countermeasures like masking or obfuscation to mitigate power side-channel vulnerabilities. Our contribution is a novel attack approach for digital CIM devices, paving the way for future research in securing these systems.
Fouwad Mir is a Ph.D. candidate in Computer Engineering at the faculty of Electrical Engineering, Mathematics and Computer Science (EEMCS), Delft University of Technology (TU-Delft). His research focuses on hardware security for novel computer architectures and neural network accelerators. He is enthusiastic about exploring hardware security vulnerabilities in digital and mixed-signal designs, aiming to develop mitigation strategies for robust and secure hardware.
Pre-Silicon Fuzzing of RISC-V Hardware Components and their Interactions
Affiliation: Delft University of Technology (NL)
In recent years, processor microarchitectures have shown both functional and security issues. Current mitigation-focused research centers around undirected testing of processors, i.e. hardware or processor fuzz testing. More recent promising studies focus on using test programs as fuzz inputs. Cascade, which is the state-of-the-art in these test program focused tools, uses a loosely integrated collection of existing tools. This severely limits what intricate behaviors and chip-component interactions it can test and the speed at which it can generate test programs. We propose a set of tightly integrated tools that allow for the real-time program generation. These tools allow for automation in the behavioral verification and security analysis of intricate interactions between chip-components.
Gijs Burghoorn finished a BSc. Computer Science at Leiden University in the Netherlands. Afterwards, he went to Grenoble in France and got a MSc. in Informatics and Cybersecurity. Here, he performed research into Hardware Security, Side-Channel Analysis and Fault Injection. Afterwards, he started his PhD at the TU Delft in the Netherlands.
Online Detection of Unique Faults in RRAMs
Affiliations: 1 Delft University of Technology (NL), 2 Aix-Marseille University (FR), 3 CognitiveIC (NL)
Due to the immature manufacturing process, Resistive Random Access Memories (RRAMs) are prone to exhibit new failure mechanisms and faults, which should be efficiently detected for high-volume production. Those unique faults are hard to detect but require specific Design-for-Test (DfT) circuit design. This paper proposes a DfT based on a parallel-reference write circuit that can detect all RRAM array faults during diagnosis, production testing, and its application in the field.
Hanzhi Xun received the B.Sc. and M.Eng. degrees from Xidian University, Xi'an, China, in 2018 and 2021, respectively. He received another M.Eng. degree form Waseda University, Kitakyushu, Japan, in 2021. He is currently working toward the Ph.D. degree at the Computer Engineering Laboratory, Delft University of Technology, Delft, The Netherlands. His research interests focus on device modeling, test, and reliability of Resistive RAMs.
Reliability Assessment and Optimization of Dynamic DNNs for Edge Accelerators
Affiliation: University of Cyprus (CY)
The urge to deploy Machine Learning (ML) algo- rithms for inference on edge devices, has created the need for efficient, resource-constrained and dependable hardware, that can be utilized according to the constraints of the underlying hardware as well as those imposed by the running applications. Recently, various types of dynamic deep neural networks have been introduced, mainly for the purpose of optimizing inference performance for real-time response systems. Such edge-based systems are often resource-constrained and are deployed in various safety-critical and/or harsh environments. Therefore, these systems have increased needs in reliability, while at the same time struggle to satisfy performance and energy requirements. This thesis will first investigate the vulnerability assessment of various dynamic deep neural networks, in order to better understand the impact of these performance optimizations on the overall reliability of the networks. Consequently, the thesis will propose various approaches to co-optimize the network design based on both performance and reliability targets. The proposed approaches will be evaluated within a newly developed simulation framework which allows for efficient yet accurate vulnerability analysis, as it considers hardware-aware software fault models.
Georgios Konstantinidis received his BSc degree in Electrical and Electronic Engineering from the Department of Electrical and Computer Engineering at the University of Cyprus and his MSc degree in Mechatronics from the department of Mechanical Engineering at the University of Leeds. He is currently a PhD student. His research interests include Machine Learning, Embedded Systems, Forecasting Algorithms and ML Accelerators.
Dependable Reconfigurable Scan Networks
Affiliation: University of Stuttgart (DE)
Today, dependable modern devices are equipped with an increasing number of extra-functional instrument to facilitate cost-efficient bring-up, debug, test, diagnosis, and adaptivity in the field and might include sensors, aging monitors and Built-In Self-Test (BIST) registers e.g. Reconfigurable Scan Networks (RSNs) provide a flexible way to access such instruments as well the device’s registers throughout the lifetime, starting from post-silicon validation (PSV) through manufacturing test and finally during in-field operation. At the same time, the dependability properties of the system can be affected through an improper RSN integration. This doctoral thesis overcomes these problems and establishes a unified method for design automation of dependable RSNs. The developed method considers the most relevant dependability aspects as robustness, testability, and security compliance.
Natalia Lylina received an M.Sc. double degree in computer science from Moscow Power Engineering Institute, Russia, and Technical University of Ilmenau, Germany. Since 2017, she has been with the Institute of Computer Architecture and Computer Engineering at the University of Stuttgart as a PhD student, and received her doctoral title (Dr. rer. nat.) in 2022. She is a Member of IEEE. Her research interests include dependable systems, test and diagnosis, and reconfigurable scan networks.
Toward Fault-Tolerant Applications on Reconfigurable Systems-on-Chip
Affiliation: Politecnico di Torino (IT)
FPGA-based System-on-Chips (SoCs) have facilitated the integration of software programmability and custom hardware acceleration. The research work focuses on accurate and efficient robustness analysis for Reconfigurable SoCs, considering their heterogeneous components and radiation induced effects. Research work includes the characterization of components, such as memories, and the comparison of different technology processes through radiation testing experiments. Novel methodologies for reliability analysis of reconfigurable systems are proposed based on programmable hardware, supporting automation, integration with the development flow, and improving understanding of the fault affecting the system. The analysis of different components, such as soft and hard processors, host-device interfacing systems, and custom hardware accelerators, is presented, considering different fault models and dedicated evaluation approaches. Research work ranges from the hardware systems to the software stack of reconfigurable SoCs, providing a comprehensive investigation of their heterogeneity and the advantages that this can provide.
CORRADO DE SIO received the M.S. degree in Computer Engineering from the University of Pisa. He received his Ph.D. from Politecnico di Torino in 2023. Currently, He works in the CAD & Reliability group of Politecnico di Torino as a PostDoC . His research interests include reconfigurable devices, radiation effects, and EDA tools for analyzing and improving the reliability and the design of embedded and reconfigurable systems applications.
SDfT: Secure Design for Testability
Affiliation: Indian Institute of Technology Bhilai (IN)
Scan-based design for Testability is the de-facto standard for chip testing, which provides high observability and test coverage by enabling direct access to chip memory elements. The scan-based Design-for-Testability (DfT) technique has also become the prime target of attackers whose aim is to extract the secret information embedded inside a chip by misusing its scan infrastructure. This thesis work performs a detailed security analysis (hardware vulnerability analysis and penetration testing) of existing defense mechanisms, discovers new vulnerabilities, and proposes a new defense mechanism against scan attacks.
Yogendra Sao received an M.Tech. in computer science and engineering from the International Institute of Information Technology Hyderabad, India, in 2011 and a Ph.D. in computer science and engineering from the Indian Institute of Technology Bhilai in 2023. He is an Assistant Engineer with Chhattisgarh State Power Distribution Company Limited, Raipur, since 2011. His research interests include hardware security and secure design for testability. He has published 9 conference and journal papers.
Design for Advanced Optical Test for Image and Photonic Sensors
Affiliations: 1 STMicroelectronics (FR), 2 LIRMM University of Montpellier / CNRS (FR)
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Julia Lefevre completed her PhD at STMicroelectronics Grenoble and the LIRMM (Laboratory of Informatic, Robotic and Microelectronics of Montpellier) in France. She graduated a master degree in microelectronic at the University of Montpellier in 2020 before to work on CMOS image sensor test, looking for innovative test techniques during her PhD. She is now working as a product engineer in the Imaging Division at STMicroelectronics and will defend her PhD in June.